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author | Korey Sewell <ksewell@umich.edu> | 2008-02-27 16:48:33 -0500 |
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committer | Korey Sewell <ksewell@umich.edu> | 2008-02-27 16:48:33 -0500 |
commit | 34715cc691e217016ccce9bd1383dac9cca7126f (patch) | |
tree | 5101e6352f059cca3bac738fcb73eac70c62f48a /src/cpu/o3 | |
parent | fcfc8b8c4ff98d69aa15fba60e723a9a1c4cda42 (diff) | |
download | gem5-34715cc691e217016ccce9bd1383dac9cca7126f.tar.xz |
Fix offset in removeThread() function so that float registers start freeing up
from the right point (#32 usually) instead of restarting at 0 and double-freeing.
Commented out assert line in free_list.hh that will check for when double-free condition
goes bad.
--HG--
extra : convert_revision : 08d5f9b6a874736e487d101e85c22aaa67bf59ae
Diffstat (limited to 'src/cpu/o3')
-rw-r--r-- | src/cpu/o3/cpu.cc | 5 | ||||
-rw-r--r-- | src/cpu/o3/free_list.hh | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 8eb17d23b..ff1ee7920 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -682,7 +682,7 @@ FullO3CPU<Impl>::removeThread(unsigned tid) } // Unbind Float Regs from Rename Map - for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { + for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { PhysRegIndex phys_reg = renameMap[tid].lookup(freg); scoreboard.unsetReg(phys_reg); @@ -695,8 +695,11 @@ FullO3CPU<Impl>::removeThread(unsigned tid) decode.squash(tid); rename.squash(squash_seq_num, tid); iew.squash(tid); + //iew.ldstQueue.squash(squash_seq_num, tid); commit.rob->squash(squash_seq_num, tid); + + assert(iew.instQueue.getCount(tid) == 0); assert(iew.ldstQueue.getCount(tid) == 0); // Reset ROB/IQ/LSQ Entries diff --git a/src/cpu/o3/free_list.hh b/src/cpu/o3/free_list.hh index 42fc0c533..d05068800 100644 --- a/src/cpu/o3/free_list.hh +++ b/src/cpu/o3/free_list.hh @@ -173,6 +173,8 @@ SimpleFreeList::addReg(PhysRegIndex freed_reg) #endif freeFloatRegs.push(freed_reg); } + + //assert(freeIntRegs.size() <= numPhysicalIntRegs); } inline void |