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authorAndreas Hansson <andreas.hansson@arm.com>2015-05-15 13:39:53 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-05-15 13:39:53 -0400
commitbd583d00f96cd6e8bb0669e2aacc9dfad1eda2b1 (patch)
treec7bdbf3c32ea7af6bc2e623cff94ce4b57f470de /src/cpu/o3
parent37aab4a1558b223e63cee1e5dd40195ddb7851c0 (diff)
downloadgem5-bd583d00f96cd6e8bb0669e2aacc9dfad1eda2b1.tar.xz
misc: Appease gcc 5.1
Three minor issues are resolved: 1. Apparently gcc 5.1 does not like negation of booleans followed by bitwise AND. 2. Somehow the compiler also gets confused and warns about NoopMachInst being unused (removing it causes compilation errors though). Most likely a compiler bug. 3. There seems to be a number of instances where loop unrolling causes false positives for the array-bounds check. For now, switch to std::array. Potentially we could disable the warning for newer gcc versions, but switching to std::array is probably a good move in any case.
Diffstat (limited to 'src/cpu/o3')
-rw-r--r--src/cpu/o3/dyn_inst.hh6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 80d502f0e..6740c601d 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -44,6 +44,8 @@
#ifndef __CPU_O3_DYN_INST_HH__
#define __CPU_O3_DYN_INST_HH__
+#include <array>
+
#include "arch/isa_traits.hh"
#include "config/the_isa.hh"
#include "cpu/o3/cpu.hh"
@@ -108,13 +110,13 @@ class BaseO3DynInst : public BaseDynInst<Impl>
protected:
/** Values to be written to the destination misc. registers. */
- MiscReg _destMiscRegVal[TheISA::MaxMiscDestRegs];
+ std::array<MiscReg, TheISA::MaxMiscDestRegs> _destMiscRegVal;
/** Indexes of the destination misc. registers. They are needed to defer
* the write accesses to the misc. registers until the commit stage, when
* the instruction is out of its speculative state.
*/
- short _destMiscRegIdx[TheISA::MaxMiscDestRegs];
+ std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx;
/** Number of destination misc. registers. */
uint8_t _numDestMiscRegs;