SE/FS: Get rid of FULL_SYSTEM in the CPU directory.

13 files changed, 165 insertions, 213 deletions

diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 47b18a3ec..51643c169 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -40,15 +40,11 @@ class DerivO3CPU(BaseCPU):
     activity = Param.Unsigned(0, "Initial count")
 
     if buildEnv['USE_CHECKER']:
-        if not buildEnv['FULL_SYSTEM']:
-            checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
-                                              exitOnError=False,
-                                              updateOnError=True,
-                                              warnOnlyOnLoadError=False),
-                                    "checker")
-        else:
-            checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
-                                              warnOnlyOnLoadError=False), "checker")
+        checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
+                                          exitOnError=False,
+                                          updateOnError=True,
+                                          warnOnlyOnLoadError=False),
+                                "checker")
         checker.itb = Parent.itb
         checker.dtb = Parent.dtb
 
diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc
index 5d0bd2ed2..b34613f68 100644
--- a/src/cpu/o3/checker_builder.cc
+++ b/src/cpu/o3/checker_builder.cc
@@ -90,11 +90,8 @@ O3CheckerParams::create()
     params->dtb = dtb;
     params->system = system;
     params->cpu_id = cpu_id;
-#if FULL_SYSTEM
     params->profile = profile;
-#else
     params->process = workload;
-#endif
 
     O3Checker *cpu = new O3Checker(params);
     return cpu;
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index ffc2c16d2..b45d37df9 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -267,13 +267,11 @@ class DefaultCommit
     void squashAfter(ThreadID tid, DynInstPtr &head_inst,
             uint64_t squash_after_seq_num);
 
-#if FULL_SYSTEM
     /** Handles processing an interrupt. */
     void handleInterrupt();
 
     /** Get fetch redirecting so we can handle an interrupt */
     void propagateInterrupt();
-#endif // FULL_SYSTEM
 
     /** Commits as many instructions as possible. */
     void commitInsts();
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 75ae87c75..c481d7b9c 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -47,7 +47,6 @@
 #include "arch/utility.hh"
 #include "base/loader/symtab.hh"
 #include "base/cp_annotate.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "config/use_checker.hh"
 #include "cpu/o3/commit.hh"
@@ -61,6 +60,7 @@
 #include "debug/O3PipeView.hh"
 #include "params/DerivO3CPU.hh"
 #include "sim/faults.hh"
+#include "sim/full_system.hh"
 
 #if USE_CHECKER
 #include "cpu/checker/cpu.hh"
@@ -148,9 +148,7 @@ DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
         pc[tid].set(0);
         lastCommitedSeqNum[tid] = 0;
     }
-#if FULL_SYSTEM
     interrupt = NoFault;
-#endif
 }
 
 template <class Impl>
@@ -700,7 +698,6 @@ DefaultCommit<Impl>::tick()
     updateStatus();
 }
 
-#if FULL_SYSTEM
 template <class Impl>
 void
 DefaultCommit<Impl>::handleInterrupt()
@@ -766,22 +763,20 @@ DefaultCommit<Impl>::propagateInterrupt()
         toIEW->commitInfo[0].interruptPending = true;
 }
 
-#endif // FULL_SYSTEM
-
 template <class Impl>
 void
 DefaultCommit<Impl>::commit()
 {
-
-#if FULL_SYSTEM
-    // Check for any interrupt that we've already squashed for and start processing it.
-    if (interrupt != NoFault)
-        handleInterrupt();
-
-    // Check if we have a interrupt and get read to handle it
-    if (cpu->checkInterrupts(cpu->tcBase(0)))
-        propagateInterrupt();
-#endif // FULL_SYSTEM
+    if (FullSystem) {
+        // Check for any interrupt that we've already squashed for and start
+        // processing it.
+        if (interrupt != NoFault)
+            handleInterrupt();
+
+        // Check if we have a interrupt and get read to handle it
+        if (cpu->checkInterrupts(cpu->tcBase(0)))
+            propagateInterrupt();
+    }
 
     ////////////////////////////////////
     // Check for any possible squashes, handle them first
@@ -1173,22 +1168,22 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 
     updateComInstStats(head_inst);
 
-#if FULL_SYSTEM
-    if (thread[tid]->profile) {
-        thread[tid]->profilePC = head_inst->instAddr();
-        ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
-                                                          head_inst->staticInst);
+    if (FullSystem) {
+        if (thread[tid]->profile) {
+            thread[tid]->profilePC = head_inst->instAddr();
+            ProfileNode *node = thread[tid]->profile->consume(
+                    thread[tid]->getTC(), head_inst->staticInst);
 
-        if (node)
-            thread[tid]->profileNode = node;
-    }
-    if (CPA::available()) {
-        if (head_inst->isControl()) {
-            ThreadContext *tc = thread[tid]->getTC();
-            CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
+            if (node)
+                thread[tid]->profileNode = node;
+        }
+        if (CPA::available()) {
+            if (head_inst->isControl()) {
+                ThreadContext *tc = thread[tid]->getTC();
+                CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
+            }
         }
     }
-#endif
     DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
             head_inst->seqNum, head_inst->pcState());
     if (head_inst->traceData) {
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 08cf0a692..16e78f8ec 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -32,7 +32,6 @@
  */
 
 #include "arch/kernel_stats.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "config/use_checker.hh"
 #include "cpu/o3/cpu.hh"
@@ -47,6 +46,7 @@
 #include "debug/Quiesce.hh"
 #include "enums/MemoryMode.hh"
 #include "sim/core.hh"
+#include "sim/full_system.hh"
 #include "sim/process.hh"
 #include "sim/stat_control.hh"
 #include "sim/system.hh"
@@ -215,18 +215,16 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
     if (params->checker) {
         BaseCPU *temp_checker = params->checker;
         checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
-#if FULL_SYSTEM
         checker->setSystem(params->system);
-#endif
     } else {
         checker = NULL;
     }
 #endif // USE_CHECKER
 
-#if !FULL_SYSTEM
-    thread.resize(numThreads);
-    tids.resize(numThreads);
-#endif
+    if (!FullSystem) {
+        thread.resize(numThreads);
+        tids.resize(numThreads);
+    }
 
     // The stages also need their CPU pointer setup.  However this
     // must be done at the upper level CPU because they have pointers
@@ -262,17 +260,18 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
     rename.setIEWStage(&iew);
     rename.setCommitStage(&commit);
 
-#if !FULL_SYSTEM
-    ThreadID active_threads = params->workload.size();
+    ThreadID active_threads;
+    if (FullSystem) {
+        active_threads = 1;
+    } else {
+        active_threads = params->workload.size();
 
-    if (active_threads > Impl::MaxThreads) {
-        panic("Workload Size too large. Increase the 'MaxThreads'"
-              "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
-              "edit your workload size.");
+        if (active_threads > Impl::MaxThreads) {
+            panic("Workload Size too large. Increase the 'MaxThreads' "
+                  "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
+                  "or edit your workload size.");
+        }
     }
-#else
-    ThreadID active_threads = 1;
-#endif
 
     //Make Sure That this a Valid Architeture
     assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
@@ -351,31 +350,31 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
     this->thread.resize(this->numThreads);
 
     for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
-#if FULL_SYSTEM
-        // SMT is not supported in FS mode yet.
-        assert(this->numThreads == 1);
-        this->thread[tid] = new Thread(this, 0, NULL);
-#else
-        if (tid < params->workload.size()) {
-            DPRINTF(O3CPU, "Workload[%i] process is %#x",
-                    tid, this->thread[tid]);
-            this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
-                    (typename Impl::O3CPU *)(this),
-                    tid, params->workload[tid]);
-
-            //usedTids[tid] = true;
-            //threadMap[tid] = tid;
+        if (FullSystem) {
+            // SMT is not supported in FS mode yet.
+            assert(this->numThreads == 1);
+            this->thread[tid] = new Thread(this, 0, NULL);
         } else {
-            //Allocate Empty thread so M5 can use later
-            //when scheduling threads to CPU
-            Process* dummy_proc = NULL;
-
-            this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
-                    (typename Impl::O3CPU *)(this),
-                    tid, dummy_proc);
-            //usedTids[tid] = false;
+            if (tid < params->workload.size()) {
+                DPRINTF(O3CPU, "Workload[%i] process is %#x",
+                        tid, this->thread[tid]);
+                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
+                        (typename Impl::O3CPU *)(this),
+                        tid, params->workload[tid]);
+
+                //usedTids[tid] = true;
+                //threadMap[tid] = tid;
+            } else {
+                //Allocate Empty thread so M5 can use later
+                //when scheduling threads to CPU
+                Process* dummy_proc = NULL;
+
+                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
+                        (typename Impl::O3CPU *)(this),
+                        tid, dummy_proc);
+                //usedTids[tid] = false;
+            }
         }
-#endif // !FULL_SYSTEM
 
         ThreadContext *tc;
 
@@ -397,10 +396,10 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
         assert(o3_tc->cpu);
         o3_tc->thread = this->thread[tid];
 
-#if FULL_SYSTEM
-        // Setup quiesce event.
-        this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
-#endif
+        if (FullSystem) {
+            // Setup quiesce event.
+            this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
+        }
         // Give the thread the TC.
         this->thread[tid]->tc = tc;
 
@@ -547,9 +546,8 @@ FullO3CPU<Impl>::tick()
 
     commit.tick();
 
-#if !FULL_SYSTEM
-    doContextSwitch();
-#endif
+    if (!FullSystem)
+        doContextSwitch();
 
     // Now advance the time buffers
     timeBuffer.advance();
@@ -581,9 +579,8 @@ FullO3CPU<Impl>::tick()
         }
     }
 
-#if !FULL_SYSTEM
-    updateThreadPriority();
-#endif
+    if (!FullSystem)
+        updateThreadPriority();
 }
 
 template <class Impl>
@@ -597,12 +594,12 @@ FullO3CPU<Impl>::init()
     for (ThreadID tid = 0; tid < numThreads; ++tid)
         thread[tid]->inSyscall = true;
 
-#if FULL_SYSTEM
-    for (ThreadID tid = 0; tid < numThreads; tid++) {
-        ThreadContext *src_tc = threadContexts[tid];
-        TheISA::initCPU(src_tc, src_tc->contextId());
+    if (FullSystem) {
+        for (ThreadID tid = 0; tid < numThreads; tid++) {
+            ThreadContext *src_tc = threadContexts[tid];
+            TheISA::initCPU(src_tc, src_tc->contextId());
+        }
     }
-#endif
 
     // Clear inSyscall.
     for (int tid = 0; tid < numThreads; ++tid)
@@ -738,11 +735,11 @@ FullO3CPU<Impl>::insertThread(ThreadID tid)
     DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
     // Will change now that the PC and thread state is internal to the CPU
     // and not in the ThreadContext.
-#if FULL_SYSTEM
-    ThreadContext *src_tc = system->threadContexts[tid];
-#else
-    ThreadContext *src_tc = tcBase(tid);
-#endif
+    ThreadContext *src_tc;
+    if (FullSystem)
+        src_tc = system->threadContexts[tid];
+    else
+        src_tc = tcBase(tid);
 
     //Bind Int Regs to Rename Map
     for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
diff --git a/src/cpu/o3/cpu_builder.cc b/src/cpu/o3/cpu_builder.cc
index 097dc7181..82df345bd 100644
--- a/src/cpu/o3/cpu_builder.cc
+++ b/src/cpu/o3/cpu_builder.cc
@@ -47,22 +47,23 @@ class DerivO3CPU : public FullO3CPU<O3CPUImpl>
 DerivO3CPU *
 DerivO3CPUParams::create()
 {
-#if FULL_SYSTEM
-    // Full-system only supports a single thread for the moment.
-    ThreadID actual_num_threads = 1;
-#else
-    if (workload.size() > numThreads) {
-        fatal("Workload Size (%i) > Max Supported Threads (%i) on This CPU",
-              workload.size(), numThreads);
-    } else if (workload.size() == 0) {
-        fatal("Must specify at least one workload!");
+    ThreadID actual_num_threads;
+    if (FullSystem) {
+        // Full-system only supports a single thread for the moment.
+        actual_num_threads = 1;
+    } else {
+        if (workload.size() > numThreads) {
+            fatal("Workload Size (%i) > Max Supported Threads (%i) on This CPU",
+                  workload.size(), numThreads);
+        } else if (workload.size() == 0) {
+            fatal("Must specify at least one workload!");
+        }
+
+        // In non-full-system mode, we infer the number of threads from
+        // the workload if it's not explicitly specified.
+        actual_num_threads =
+            (numThreads >= workload.size()) ? numThreads : workload.size();
     }
-    
-    // In non-full-system mode, we infer the number of threads from
-    // the workload if it's not explicitly specified.
-    ThreadID actual_num_threads =
-        (numThreads >= workload.size()) ? numThreads : workload.size();
-#endif
 
     numThreads = actual_num_threads;
 
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 0c0ec768e..3def971e9 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -30,13 +30,13 @@
 
 #include "arch/types.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/decode.hh"
 #include "cpu/inst_seq.hh"
 #include "debug/Activity.hh"
 #include "debug/Decode.hh"
 #include "params/DerivO3CPU.hh"
+#include "sim/full_system.hh"
 
 using namespace std;
 
@@ -322,19 +322,18 @@ DefaultDecode<Impl>::squash(ThreadID tid)
 
     if (decodeStatus[tid] == Blocked ||
         decodeStatus[tid] == Unblocking) {
-#if !FULL_SYSTEM
-        // In syscall emulation, we can have both a block and a squash due
-        // to a syscall in the same cycle.  This would cause both signals to
-        // be high.  This shouldn't happen in full system.
-        // @todo: Determine if this still happens.
-        if (toFetch->decodeBlock[tid]) {
-            toFetch->decodeBlock[tid] = 0;
-        } else {
+        if (FullSystem) {
             toFetch->decodeUnblock[tid] = 1;
+        } else {
+            // In syscall emulation, we can have both a block and a squash due
+            // to a syscall in the same cycle.  This would cause both signals
+            // to be high.  This shouldn't happen in full system.
+            // @todo: Determine if this still happens.
+            if (toFetch->decodeBlock[tid])
+                toFetch->decodeBlock[tid] = 0;
+            else
+                toFetch->decodeUnblock[tid] = 1;
         }
-#else
-        toFetch->decodeUnblock[tid] = 1;
-#endif
     }
 
     // Set status to squashing.
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index b0ec349dc..686b40dc5 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -45,7 +45,9 @@
 #include <cstring>
 
 #include "arch/isa_traits.hh"
+#include "arch/tlb.hh"
 #include "arch/utility.hh"
+#include "arch/vtophys.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
 #include "config/use_checker.hh"
@@ -61,12 +63,8 @@
 #include "sim/byteswap.hh"
 #include "sim/core.hh"
 #include "sim/eventq.hh"
-
-#if FULL_SYSTEM
-#include "arch/tlb.hh"
-#include "arch/vtophys.hh"
+#include "sim/full_system.hh"
 #include "sim/system.hh"
-#endif // FULL_SYSTEM
 
 using namespace std;
 
@@ -907,15 +905,15 @@ DefaultFetch<Impl>::tick()
 
     DPRINTF(Fetch, "Running stage.\n");
 
-    #if FULL_SYSTEM
-    if (fromCommit->commitInfo[0].interruptPending) {
-        interruptPending = true;
-    }
+    if (FullSystem) {
+        if (fromCommit->commitInfo[0].interruptPending) {
+            interruptPending = true;
+        }
 
-    if (fromCommit->commitInfo[0].clearInterrupt) {
-        interruptPending = false;
+        if (fromCommit->commitInfo[0].clearInterrupt) {
+            interruptPending = false;
+        }
     }
-#endif
 
     for (threadFetched = 0; threadFetched < numFetchingThreads;
          threadFetched++) {
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 14917bc16..1fcd73ba1 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -334,10 +334,8 @@ class LSQ {
     /** D-cache port. */
     DcachePort dcachePort;
 
-#if FULL_SYSTEM
     /** Tell the CPU to update the Phys and Virt ports. */
     void updateMemPorts() { cpu->updateMemPorts(); }
-#endif
 
   protected:
     /** The LSQ policy for SMT mode. */
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index ef9167d8c..8b1638c70 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -46,11 +46,9 @@ LSQ<Impl>::DcachePort::setPeer(Port *port)
 {
     Port::setPeer(port);
 
-#if FULL_SYSTEM
     // Update the ThreadContext's memory ports (Functional/Virtual
     // Ports)
     lsq->updateMemPorts();
-#endif
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index d04f45cc0..ec3a252fd 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -35,6 +35,7 @@
 #include <vector>
 
 #include "arch/isa_traits.hh"
+#include "arch/kernel_stats.hh"
 #include "arch/types.hh"
 #include "base/trace.hh"
 #include "config/full_system.hh"
@@ -42,10 +43,6 @@
 #include "cpu/o3/comm.hh"
 #include "debug/IEW.hh"
 
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
-#endif
-
 /**
  * Simple physical register file class.
  * Right now this is specific to Alpha until we decide if/how to make things
@@ -174,10 +171,8 @@ class PhysRegFile
     /** Floating point register file. */
     PhysFloatReg *floatRegFile;
 
-#if FULL_SYSTEM
   private:
     int intrflag;                       // interrupt flag
-#endif
 
   private:
     /** CPU pointer. */
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index a49440f1f..15fc397dc 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -41,6 +41,7 @@
  *          Korey Sewell
  */
 
+#include "arch/kernel_stats.hh"
 #include "arch/registers.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/thread_context.hh"
@@ -66,9 +67,7 @@ void
 O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
 {
     // some things should already be set up
-#if FULL_SYSTEM
     assert(getSystemPtr() == old_context->getSystemPtr());
-#endif
     assert(getProcessPtr() == old_context->getProcessPtr());
 
     // copy over functional state
@@ -77,24 +76,23 @@ O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
     setContextId(old_context->contextId());
     setThreadId(old_context->threadId());
 
-#if !FULL_SYSTEM
-    thread->funcExeInst = old_context->readFuncExeInst();
-#else
-    EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
-    if (other_quiesce) {
-        // Point the quiesce event's TC at this TC so that it wakes up
-        // the proper CPU.
-        other_quiesce->tc = this;
+    if (FullSystem) {
+        EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
+        if (other_quiesce) {
+            // Point the quiesce event's TC at this TC so that it wakes up
+            // the proper CPU.
+            other_quiesce->tc = this;
+        }
+        if (thread->quiesceEvent) {
+            thread->quiesceEvent->tc = this;
+        }
+
+        // Transfer kernel stats from one CPU to the other.
+        thread->kernelStats = old_context->getKernelStats();
+        cpu->lockFlag = false;
+    } else {
+        thread->funcExeInst = old_context->readFuncExeInst();
     }
-    if (thread->quiesceEvent) {
-        thread->quiesceEvent->tc = this;
-    }
-
-    // Transfer kernel stats from one CPU to the other.
-    thread->kernelStats = old_context->getKernelStats();
-//    storeCondFailures = 0;
-    cpu->lockFlag = false;
-#endif
 
     old_context->setStatus(ThreadContext::Halted);
 
@@ -112,10 +110,7 @@ O3ThreadContext<Impl>::activate(int delay)
     if (thread->status() == ThreadContext::Active)
         return;
 
-#if FULL_SYSTEM
     thread->lastActivate = curTick();
-#endif
-
     thread->setStatus(ThreadContext::Active);
 
     // status() == Suspended
@@ -132,19 +127,9 @@ O3ThreadContext<Impl>::suspend(int delay)
     if (thread->status() == ThreadContext::Suspended)
         return;
 
-#if FULL_SYSTEM
     thread->lastActivate = curTick();
     thread->lastSuspend = curTick();
-#endif
-/*
-#if FULL_SYSTEM
-    // Don't change the status from active if there are pending interrupts
-    if (cpu->checkInterrupts()) {
-        assert(status() == ThreadContext::Active);
-        return;
-    }
-#endif
-*/
+
     thread->setStatus(ThreadContext::Suspended);
     cpu->suspendContext(thread->threadId());
 }
@@ -167,32 +152,26 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::regStats(const std::string &name)
 {
-#if FULL_SYSTEM
-    thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
-    thread->kernelStats->regStats(name + ".kern");
-#endif
+    if (FullSystem) {
+        thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
+        thread->kernelStats->regStats(name + ".kern");
+    }
 }
 
 template <class Impl>
 void
 O3ThreadContext<Impl>::serialize(std::ostream &os)
 {
-#if FULL_SYSTEM
-    if (thread->kernelStats)
+    if (FullSystem && thread->kernelStats)
         thread->kernelStats->serialize(os);
-#endif
-
 }
 
 template <class Impl>
 void
 O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string &section)
 {
-#if FULL_SYSTEM
-    if (thread->kernelStats)
+    if (FullSystem && thread->kernelStats)
         thread->kernelStats->unserialize(cp, section);
-#endif
-
 }
 
 template <class Impl>
@@ -232,9 +211,8 @@ O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
     TheISA::copyRegs(tc, this);
     thread->inSyscall = false;
 
-#if !FULL_SYSTEM
-    this->thread->funcExeInst = tc->readFuncExeInst();
-#endif
+    if (!FullSystem)
+        this->thread->funcExeInst = tc->readFuncExeInst();
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index 1d58e2b27..fc54ec33c 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -35,6 +35,7 @@
 #include "base/output.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
+#include "sim/full_system.hh"
 #include "sim/sim_exit.hh"
 
 class EndQuiesceEvent;
@@ -74,21 +75,22 @@ struct O3ThreadState : public ThreadState {
         : ThreadState(_cpu, _thread_num, _process),
           cpu(_cpu), inSyscall(0), trapPending(0)
     {
-#if FULL_SYSTEM
-        if (cpu->params()->profile) {
-            profile = new FunctionProfile(cpu->params()->system->kernelSymtab);
-            Callback *cb =
-                new MakeCallback<O3ThreadState,
-                &O3ThreadState::dumpFuncProfile>(this);
-            registerExitCallback(cb);
-        }
+        if (FullSystem) {
+            if (cpu->params()->profile) {
+                profile = new FunctionProfile(
+                        cpu->params()->system->kernelSymtab);
+                Callback *cb =
+                    new MakeCallback<O3ThreadState,
+                    &O3ThreadState::dumpFuncProfile>(this);
+                registerExitCallback(cb);
+            }
 
-        // let's fill with a dummy node for now so we don't get a segfault
-        // on the first cycle when there's no node available.
-        static ProfileNode dummyNode;
-        profileNode = &dummyNode;
-        profilePC = 3;
-#endif
+            // let's fill with a dummy node for now so we don't get a segfault
+            // on the first cycle when there's no node available.
+            static ProfileNode dummyNode;
+            profileNode = &dummyNode;
+            profilePC = 3;
+        }
     }
 
     /** Pointer to the ThreadContext of this thread. */