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authorAli Saidi <saidi@eecs.umich.edu>2007-06-01 14:55:17 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-06-01 14:55:17 -0400
commit66ee27078eed95843c5994f0457d199c2317d752 (patch)
tree8ad9c0a6ec48aee3bbef22d0604fbbb10ce6fd22 /src/cpu/o3
parent6e8a06b237ef77e34cd8b01b2ba80bdd672c6aae (diff)
parentbe0aef981943d123e0f4eb8c5520a74c1eb1002a (diff)
downloadgem5-66ee27078eed95843c5994f0457d199c2317d752.tar.xz
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 43dc3a23758e7956572d59464ebddcc56e82728b
Diffstat (limited to 'src/cpu/o3')
-rw-r--r--src/cpu/o3/fetch_impl.hh4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index e16f97558..895b4a46c 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1151,10 +1151,14 @@ DefaultFetch<Impl>::fetch(bool &status_change)
DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
tid, instruction->staticInst->disassemble(fetch_PC));
+#if TRACING_ON
instruction->traceData =
Trace::getInstRecord(curTick, cpu->tcBase(tid),
instruction->staticInst,
instruction->readPC());
+#elif
+ instruction->traceData = NULL;
+#endif
///FIXME This needs to be more robust in dealing with delay slots
#if !ISA_HAS_DELAY_SLOT