Merge zizzer.eecs.umich.edu:/bk/newmem

into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem

--HG--
extra : convert_revision : d764fe37c71269a04fcede6cbf30e24262447e89

13 files changed, 88 insertions, 88 deletions

diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh
index 4a2086296..676893098 100644
--- a/src/cpu/o3/alpha/cpu.hh
+++ b/src/cpu/o3/alpha/cpu.hh
@@ -106,21 +106,21 @@ class AlphaO3CPU : public FullO3CPU<Impl>
 
 #endif
     /** Reads a miscellaneous register. */
-    TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
+    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
 
     /** Reads a misc. register, including any side effects the read
      * might have as defined by the architecture.
      */
-    TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
+    TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
 
     /** Sets a miscellaneous register. */
-    void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
+    void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
             unsigned tid);
 
     /** Sets a misc. register, including any side effects the write
      * might have as defined by the architecture.
      */
-    void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val,
+    void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
             unsigned tid);
 
     /** Initiates a squash of all in-flight instructions for a given
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index 41f149963..b91972704 100644
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -154,32 +154,32 @@ AlphaO3CPU<Impl>::regStats()
 
 template <class Impl>
 TheISA::MiscReg
-AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
+AlphaO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscReg(misc_reg, tid);
+    return this->regFile.readMiscRegNoEffect(misc_reg, tid);
 }
 
 template <class Impl>
 TheISA::MiscReg
-AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
+AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscRegWithEffect(misc_reg, tid);
+    return this->regFile.readMiscReg(misc_reg, tid);
 }
 
 template <class Impl>
 void
-AlphaO3CPU<Impl>::setMiscReg(int misc_reg, const TheISA::MiscReg &val,
+AlphaO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
         unsigned tid)
 {
-    this->regFile.setMiscReg(misc_reg, val, tid);
+    this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
 }
 
 template <class Impl>
 void
-AlphaO3CPU<Impl>::setMiscRegWithEffect(int misc_reg,
+AlphaO3CPU<Impl>::setMiscReg(int misc_reg,
         const TheISA::MiscReg &val, unsigned tid)
 {
-    this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
+    this->regFile.setMiscReg(misc_reg, val, tid);
 }
 
 template <class Impl>
@@ -209,7 +209,7 @@ Fault
 AlphaO3CPU<Impl>::hwrei(unsigned tid)
 {
     // Need to clear the lock flag upon returning from an interrupt.
-    this->setMiscReg(AlphaISA::MISCREG_LOCKFLAG, false, tid);
+    this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
 
     this->thread[tid]->kernelStats->hwrei();
 
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index 603a1b52d..6c27e890a 100644
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -95,39 +95,39 @@ class AlphaDynInst : public BaseDynInst<Impl>
 
   public:
     /** Reads a miscellaneous register. */
-    MiscReg readMiscReg(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg)
     {
-        return this->cpu->readMiscReg(misc_reg, this->threadNumber);
+        return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber);
     }
 
     /** Reads a misc. register, including any side-effects the read
      * might have as defined by the architecture.
      */
-    MiscReg readMiscRegWithEffect(int misc_reg)
+    MiscReg readMiscReg(int misc_reg)
     {
-        return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
+        return this->cpu->readMiscReg(misc_reg, this->threadNumber);
     }
 
     /** Sets a misc. register. */
-    void setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
     {
         this->instResult.integer = val;
-        return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
+        return this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber);
     }
 
     /** Sets a misc. register, including any side-effects the write
      * might have as defined by the architecture.
      */
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
-        return this->cpu->setMiscRegWithEffect(misc_reg, val,
+        return this->cpu->setMiscReg(misc_reg, val,
                                                this->threadNumber);
     }
 
     /** Reads a miscellaneous register. */
     TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
     {
-        return this->cpu->readMiscReg(
+        return this->cpu->readMiscRegNoEffect(
                 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 this->threadNumber);
     }
@@ -137,7 +137,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
      */
     TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
     {
-        return this->cpu->readMiscRegWithEffect(
+        return this->cpu->readMiscReg(
                 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 this->threadNumber);
     }
@@ -146,7 +146,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
     void setMiscRegOperand(const StaticInst * si, int idx, const MiscReg &val)
     {
         this->instResult.integer = val;
-        return this->cpu->setMiscReg(
+        return this->cpu->setMiscRegNoEffect(
                 si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 val, this->threadNumber);
     }
@@ -157,7 +157,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
     void setMiscRegOperandWithEffect(const StaticInst *si, int idx,
                                      const MiscReg &val)
     {
-        return this->cpu->setMiscRegWithEffect(
+        return this->cpu->setMiscReg(
                 si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 val, this->threadNumber);
     }
diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh
index 50cdec408..fdce1ade5 100644
--- a/src/cpu/o3/alpha/dyn_inst_impl.hh
+++ b/src/cpu/o3/alpha/dyn_inst_impl.hh
@@ -118,7 +118,7 @@ AlphaDynInst<Impl>::hwrei()
         return new AlphaISA::UnimplementedOpcodeFault;
 
     // Set the next PC based on the value of the EXC_ADDR IPR.
-    this->setNextPC(this->cpu->readMiscReg(AlphaISA::IPR_EXC_ADDR,
+    this->setNextPC(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
                                            this->threadNumber));
 
     // Tell CPU to clear any state it needs to if a hwrei is taken.
diff --git a/src/cpu/o3/mips/cpu.hh b/src/cpu/o3/mips/cpu.hh
index 7e6268cdf..0361c1814 100755
--- a/src/cpu/o3/mips/cpu.hh
+++ b/src/cpu/o3/mips/cpu.hh
@@ -87,20 +87,20 @@ class MipsO3CPU : public FullO3CPU<Impl>
     }
 
     /** Reads a miscellaneous register. */
-    TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
+    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
 
     /** Reads a misc. register, including any side effects the read
      * might have as defined by the architecture.
      */
-    TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
+    TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
 
     /** Sets a miscellaneous register. */
-    void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
+    void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
 
     /** Sets a misc. register, including any side effects the write
      * might have as defined by the architecture.
      */
-    void setMiscRegWithEffect(int misc_reg,
+    void setMiscReg(int misc_reg,
             const TheISA::MiscReg &val, unsigned tid);
 
     /** Initiates a squash of all in-flight instructions for a given
diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh
index e7dbd3aba..317fd748e 100644
--- a/src/cpu/o3/mips/cpu_impl.hh
+++ b/src/cpu/o3/mips/cpu_impl.hh
@@ -135,31 +135,31 @@ MipsO3CPU<Impl>::regStats()
 
 template <class Impl>
 MiscReg
-MipsO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
+MipsO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscReg(misc_reg, tid);
+    return this->regFile.readMiscRegNoEffect(misc_reg, tid);
 }
 
 template <class Impl>
 MiscReg
-MipsO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
+MipsO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscRegWithEffect(misc_reg, tid);
+    return this->regFile.readMiscReg(misc_reg, tid);
 }
 
 template <class Impl>
 void
-MipsO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
+MipsO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid)
 {
-    this->regFile.setMiscReg(misc_reg, val, tid);
+    this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
 }
 
 template <class Impl>
 void
-MipsO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
+MipsO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val,
                                        unsigned tid)
 {
-    this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
+    this->regFile.setMiscReg(misc_reg, val, tid);
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh
index f53530908..366b4bb23 100755
--- a/src/cpu/o3/mips/dyn_inst.hh
+++ b/src/cpu/o3/mips/dyn_inst.hh
@@ -93,32 +93,32 @@ class MipsDynInst : public BaseDynInst<Impl>
 
   public:
     /** Reads a miscellaneous register. */
-    MiscReg readMiscReg(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg)
     {
-        return this->cpu->readMiscReg(misc_reg, this->threadNumber);
+        return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber);
     }
 
     /** Reads a misc. register, including any side-effects the read
      * might have as defined by the architecture.
      */
-    MiscReg readMiscRegWithEffect(int misc_reg)
+    MiscReg readMiscReg(int misc_reg)
     {
-        return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
+        return this->cpu->readMiscReg(misc_reg, this->threadNumber);
     }
 
     /** Sets a misc. register. */
-    void setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
     {
         this->instResult.integer = val;
-        this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
+        this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber);
     }
 
     /** Sets a misc. register, including any side-effects the write
      * might have as defined by the architecture.
      */
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
-        return this->cpu->setMiscRegWithEffect(misc_reg, val,
+        return this->cpu->setMiscReg(misc_reg, val,
                                                this->threadNumber);
     }
 
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 598af123e..c4f8f3a9f 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -225,26 +225,26 @@ class PhysRegFile
         floatRegFile[reg_idx].q = val;
     }
 
-    MiscReg readMiscReg(int misc_reg, unsigned thread_id)
+    MiscReg readMiscRegNoEffect(int misc_reg, unsigned thread_id)
     {
-        return miscRegs[thread_id].readReg(misc_reg);
+        return miscRegs[thread_id].readRegNoEffect(misc_reg);
     }
 
-    MiscReg readMiscRegWithEffect(int misc_reg, unsigned thread_id)
+    MiscReg readMiscReg(int misc_reg, unsigned thread_id)
     {
-        return miscRegs[thread_id].readRegWithEffect(misc_reg,
+        return miscRegs[thread_id].readReg(misc_reg,
                                                      cpu->tcBase(thread_id));
     }
 
-    void setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned thread_id)
     {
-        miscRegs[thread_id].setReg(misc_reg, val);
+        miscRegs[thread_id].setRegNoEffect(misc_reg, val);
     }
 
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val,
+    void setMiscReg(int misc_reg, const MiscReg &val,
                                unsigned thread_id)
     {
-        miscRegs[thread_id].setRegWithEffect(misc_reg, val,
+        miscRegs[thread_id].setReg(misc_reg, val,
                                                     cpu->tcBase(thread_id));
     }
 
diff --git a/src/cpu/o3/sparc/cpu.hh b/src/cpu/o3/sparc/cpu.hh
index 08ebd2710..7b932e429 100644
--- a/src/cpu/o3/sparc/cpu.hh
+++ b/src/cpu/o3/sparc/cpu.hh
@@ -106,20 +106,20 @@ class SparcO3CPU : public FullO3CPU<Impl>
 
 #endif
     /** Reads a miscellaneous register. */
-    TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
+    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
 
     /** Reads a misc. register, including any side effects the read
      * might have as defined by the architecture.
      */
-    TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
+    TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
 
     /** Sets a miscellaneous register. */
-    void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
+    void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
 
     /** Sets a misc. register, including any side effects the write
      * might have as defined by the architecture.
      */
-    void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val,
+    void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
             unsigned tid);
 
     /** Initiates a squash of all in-flight instructions for a given
diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh
index c039a8fec..a425a8a56 100644
--- a/src/cpu/o3/sparc/cpu_impl.hh
+++ b/src/cpu/o3/sparc/cpu_impl.hh
@@ -153,32 +153,32 @@ SparcO3CPU<Impl>::regStats()
 
 template <class Impl>
 TheISA::MiscReg
-SparcO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
+SparcO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscReg(misc_reg, tid);
+    return this->regFile.readMiscRegNoEffect(misc_reg, tid);
 }
 
 template <class Impl>
 TheISA::MiscReg
-SparcO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
+SparcO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscRegWithEffect(misc_reg, tid);
+    return this->regFile.readMiscReg(misc_reg, tid);
 }
 
 template <class Impl>
 void
-SparcO3CPU<Impl>::setMiscReg(int misc_reg,
+SparcO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
         const SparcISA::MiscReg &val, unsigned tid)
 {
-    this->regFile.setMiscReg(misc_reg, val, tid);
+    this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
 }
 
 template <class Impl>
 void
-SparcO3CPU<Impl>::setMiscRegWithEffect(int misc_reg,
+SparcO3CPU<Impl>::setMiscReg(int misc_reg,
         const SparcISA::MiscReg &val, unsigned tid)
 {
-    this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
+    this->regFile.setMiscReg(misc_reg, val, tid);
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/sparc/dyn_inst.hh b/src/cpu/o3/sparc/dyn_inst.hh
index 4314488b5..bd61b0384 100644
--- a/src/cpu/o3/sparc/dyn_inst.hh
+++ b/src/cpu/o3/sparc/dyn_inst.hh
@@ -77,39 +77,39 @@ class SparcDynInst : public BaseDynInst<Impl>
 
   public:
     /** Reads a miscellaneous register. */
-    TheISA::MiscReg readMiscReg(int misc_reg)
+    TheISA::MiscReg readMiscRegNoEffect(int misc_reg)
     {
-        return this->cpu->readMiscReg(misc_reg, this->threadNumber);
+        return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber);
     }
 
     /** Reads a misc. register, including any side-effects the read
      * might have as defined by the architecture.
      */
-    TheISA::MiscReg readMiscRegWithEffect(int misc_reg)
+    TheISA::MiscReg readMiscReg(int misc_reg)
     {
-        return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
+        return this->cpu->readMiscReg(misc_reg, this->threadNumber);
     }
 
     /** Sets a misc. register. */
-    void setMiscReg(int misc_reg, const TheISA::MiscReg &val)
+    void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val)
     {
         this->instResult.integer = val;
-        return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
+        return this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber);
     }
 
     /** Sets a misc. register, including any side-effects the write
      * might have as defined by the architecture.
      */
-    void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val)
+    void setMiscReg(int misc_reg, const TheISA::MiscReg &val)
     {
-        return this->cpu->setMiscRegWithEffect(misc_reg, val,
+        return this->cpu->setMiscReg(misc_reg, val,
                                                this->threadNumber);
     }
 
     /** Reads a miscellaneous register. */
     TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
     {
-        return this->cpu->readMiscReg(
+        return this->cpu->readMiscRegNoEffect(
                 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 this->threadNumber);
     }
@@ -119,7 +119,7 @@ class SparcDynInst : public BaseDynInst<Impl>
      */
     TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
     {
-        return this->cpu->readMiscRegWithEffect(
+        return this->cpu->readMiscReg(
                 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 this->threadNumber);
     }
@@ -129,7 +129,7 @@ class SparcDynInst : public BaseDynInst<Impl>
             int idx, const TheISA::MiscReg &val)
     {
         this->instResult.integer = val;
-        return this->cpu->setMiscReg(
+        return this->cpu->setMiscRegNoEffect(
                 si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 val, this->threadNumber);
     }
@@ -140,7 +140,7 @@ class SparcDynInst : public BaseDynInst<Impl>
     void setMiscRegOperandWithEffect(
             const StaticInst *si, int idx, const TheISA::MiscReg &val)
     {
-        return this->cpu->setMiscRegWithEffect(
+        return this->cpu->setMiscReg(
                 si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
                 val, this->threadNumber);
     }
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 4987d6eb4..93638673b 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -206,20 +206,20 @@ class O3ThreadContext : public ThreadContext
     virtual void setNextPC(uint64_t val);
 
     /** Reads a miscellaneous register. */
-    virtual MiscReg readMiscReg(int misc_reg)
-    { return cpu->readMiscReg(misc_reg, thread->readTid()); }
+    virtual MiscReg readMiscRegNoEffect(int misc_reg)
+    { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
 
     /** Reads a misc. register, including any side-effects the
      * read might have as defined by the architecture. */
-    virtual MiscReg readMiscRegWithEffect(int misc_reg)
-    { return cpu->readMiscRegWithEffect(misc_reg, thread->readTid()); }
+    virtual MiscReg readMiscReg(int misc_reg)
+    { return cpu->readMiscReg(misc_reg, thread->readTid()); }
 
     /** Sets a misc. register. */
-    virtual void setMiscReg(int misc_reg, const MiscReg &val);
+    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 
     /** Sets a misc. register, including any side-effects the
      * write might have as defined by the architecture. */
-    virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+    virtual void setMiscReg(int misc_reg, const MiscReg &val);
 
     /** Returns the number of consecutive store conditional failures. */
     // @todo: Figure out where these store cond failures should go.
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index af98fa1f5..d2acc6232 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -442,9 +442,9 @@ O3ThreadContext<Impl>::setNextPC(uint64_t val)
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
+O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 {
-    cpu->setMiscReg(misc_reg, val, thread->readTid());
+    cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid());
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
@@ -454,10 +454,10 @@ O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setMiscRegWithEffect(int misc_reg,
+O3ThreadContext<Impl>::setMiscReg(int misc_reg,
                                                 const MiscReg &val)
 {
-    cpu->setMiscRegWithEffect(misc_reg, val, thread->readTid());
+    cpu->setMiscReg(misc_reg, val, thread->readTid());
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {