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authorAli Saidi <Ali.Saidi@ARM.com>2011-01-18 16:30:02 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2011-01-18 16:30:02 -0600
commit0f9a3671b6d12f887501bc80ca50bb23c383686d (patch)
tree5406b672b12e85c0654362272350cb50057be595 /src/cpu/o3
parent96375409ea7a5593ddd7f4f723db349921f35142 (diff)
downloadgem5-0f9a3671b6d12f887501bc80ca50bb23c383686d.tar.xz
ARM: Add support for moving predicated false dest operands from sources.
Diffstat (limited to 'src/cpu/o3')
-rw-r--r--src/cpu/o3/dyn_inst.hh12
-rw-r--r--src/cpu/o3/iew_impl.hh2
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh5
3 files changed, 19 insertions, 0 deletions
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index b62068111..487c284e6 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -181,6 +181,18 @@ class BaseO3DynInst : public BaseDynInst<Impl>
this->thread->inSyscall = in_syscall;
}
+ void forwardOldRegs()
+ {
+
+ for (int idx = 0; idx < this->numDestRegs(); idx++) {
+ PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
+ TheISA::RegIndex original_dest_reg = this->staticInst->destRegIdx(idx);
+ if (original_dest_reg < TheISA::FP_Base_DepTag)
+ this->setIntRegOperand(this->staticInst.get(), idx, this->cpu->readIntReg(prev_phys_reg));
+ else if (original_dest_reg < TheISA::Ctrl_Base_DepTag)
+ this->setFloatRegOperandBits(this->staticInst.get(), idx, this->cpu->readFloatRegBits(prev_phys_reg));
+ }
+ }
#if FULL_SYSTEM
/** Calls hardware return from error interrupt. */
Fault hwrei();
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 2acb941e0..e1af20852 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -1261,6 +1261,8 @@ DefaultIEW<Impl>::executeInsts()
// will be replaced and we will lose it.
if (inst->getFault() == NoFault) {
inst->execute();
+ if (inst->readPredicate() == false)
+ inst->forwardOldRegs();
}
inst->setExecuted();
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 64d674666..7be5e4e5b 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -458,6 +458,8 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
// realizes there is activity.
// Mark it as executed unless it is an uncached load that
// needs to hit the head of commit.
+ if (inst->readPredicate() == false)
+ inst->forwardOldRegs();
DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n",
inst->seqNum,
(load_fault != NoFault ? "fault" : "predication"));
@@ -530,6 +532,9 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
Fault store_fault = store_inst->initiateAcc();
+ if (store_inst->readPredicate() == false)
+ store_inst->forwardOldRegs();
+
if (storeQueue[store_idx].size == 0) {
DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n",
store_inst->pcState(), store_inst->seqNum);