arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700

9 files changed, 120 insertions, 141 deletions

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 8d38ed1f2..a2d8147ea 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -788,29 +788,27 @@ FullO3CPU<Impl>::insertThread(ThreadID tid)
         src_tc = tcBase(tid);
 
     //Bind Int Regs to Rename Map
-    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
-        PhysRegIndex phys_reg = freeList.getIntReg();
 
-        renameMap[tid].setEntry(ireg,phys_reg);
+    for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
+         reg_id.regIdx++) {
+        PhysRegIndex phys_reg = freeList.getIntReg();
+        renameMap[tid].setEntry(reg_id, phys_reg);
         scoreboard.setReg(phys_reg);
     }
 
     //Bind Float Regs to Rename Map
-    int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
-    for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
+    for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
+         reg_id.regIdx++) {
         PhysRegIndex phys_reg = freeList.getFloatReg();
-
-        renameMap[tid].setEntry(freg,phys_reg);
+        renameMap[tid].setEntry(reg_id, phys_reg);
         scoreboard.setReg(phys_reg);
     }
 
     //Bind condition-code Regs to Rename Map
-    max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
-    for (int creg = TheISA::CC_Reg_Base;
-         creg < max_reg; creg++) {
+    for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
+         reg_id.regIdx++) {
         PhysRegIndex phys_reg = freeList.getCCReg();
-
-        renameMap[tid].setEntry(creg,phys_reg);
+        renameMap[tid].setEntry(reg_id, phys_reg);
         scoreboard.setReg(phys_reg);
     }
 
@@ -845,24 +843,25 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
     // in SMT workloads.
 
     // Unbind Int Regs from Rename Map
-    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
-        PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
+    for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
+         reg_id.regIdx++) {
+        PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
         scoreboard.unsetReg(phys_reg);
         freeList.addReg(phys_reg);
     }
 
     // Unbind Float Regs from Rename Map
-    int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
-    for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
-        PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
+    for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
+         reg_id.regIdx++) {
+        PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
         scoreboard.unsetReg(phys_reg);
         freeList.addReg(phys_reg);
     }
 
     // Unbind condition-code Regs from Rename Map
-    max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
-    for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) {
-        PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
+    for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
+         reg_id.regIdx++) {
+        PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
         scoreboard.unsetReg(phys_reg);
         freeList.addReg(phys_reg);
     }
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 8ab9979d2..3096e5946 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -67,15 +67,13 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     typedef TheISA::MachInst MachInst;
     /** Extended machine instruction type. */
     typedef TheISA::ExtMachInst ExtMachInst;
-    /** Logical register index type. */
-    typedef TheISA::RegIndex RegIndex;
-    /** Integer register index type. */
+    /** Register types. */
     typedef TheISA::IntReg   IntReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
     typedef TheISA::CCReg   CCReg;
 
-    /** Misc register index type. */
+    /** Misc register type. */
     typedef TheISA::MiscReg  MiscReg;
 
     enum {
@@ -172,9 +170,9 @@ class BaseO3DynInst : public BaseDynInst<Impl>
      */
     TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
     {
-        return this->cpu->readMiscReg(
-                si->srcRegIdx(idx) - TheISA::Misc_Reg_Base,
-                this->threadNumber);
+        RegId reg = si->srcRegIdx(idx);
+        assert(reg.regClass == MiscRegClass);
+        return this->cpu->readMiscReg(reg.regIdx, this->threadNumber);
     }
 
     /** Sets a misc. register, including any side-effects the write
@@ -183,8 +181,9 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     void setMiscRegOperand(const StaticInst *si, int idx,
                                      const MiscReg &val)
     {
-        int misc_reg = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
-        setMiscReg(misc_reg, val);
+        RegId reg =  si->destRegIdx(idx);
+        assert(reg.regClass == MiscRegClass);
+        setMiscReg(reg.regIdx, val);
     }
 
     /** Called at the commit stage to update the misc. registers. */
@@ -209,9 +208,9 @@ class BaseO3DynInst : public BaseDynInst<Impl>
 
         for (int idx = 0; idx < this->numDestRegs(); idx++) {
             PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
-            TheISA::RegIndex original_dest_reg =
+            RegId original_dest_reg =
                 this->staticInst->destRegIdx(idx);
-            switch (regIdxToClass(original_dest_reg)) {
+            switch (original_dest_reg.regClass) {
               case IntRegClass:
                 this->setIntRegOperand(this->staticInst.get(), idx,
                                        this->cpu->readIntReg(prev_phys_reg));
@@ -301,13 +300,13 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     }
 
 #if THE_ISA == MIPS_ISA
-    MiscReg readRegOtherThread(int misc_reg, ThreadID tid)
+    MiscReg readRegOtherThread(RegId misc_reg, ThreadID tid)
     {
         panic("MIPS MT not defined for O3 CPU.\n");
         return 0;
     }
 
-    void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid)
+    void setRegOtherThread(RegId misc_reg, MiscReg val, ThreadID tid)
     {
         panic("MIPS MT not defined for O3 CPU.\n");
     }
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 00bcb3345..f6a42c398 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -110,11 +110,11 @@ BaseO3DynInst<Impl>::initVars()
     // as the normal register entries.  It will allow the IQ to work
     // without any modifications.
     for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
-        this->_destRegIdx[i] = this->staticInst->destRegIdx(i);
+        this->_destRegIdx[i] = this->staticInst->destRegIdx(i).regIdx;
     }
 
     for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
-        this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
+        this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i).regIdx;
     }
 
     this->_readySrcRegIdx.reset();
diff --git a/src/cpu/o3/probe/elastic_trace.cc b/src/cpu/o3/probe/elastic_trace.cc
index c97bf7877..05b16805f 100644
--- a/src/cpu/o3/probe/elastic_trace.cc
+++ b/src/cpu/o3/probe/elastic_trace.cc
@@ -262,15 +262,15 @@ ElasticTrace::updateRegDep(const DynInstPtr &dyn_inst)
     for (int dest_idx = 0; dest_idx < max_regs; dest_idx++) {
         // For data dependency tracking the register must be an int, float or
         // CC register and not a Misc register.
-        TheISA::RegIndex dest_reg = dyn_inst->destRegIdx(dest_idx);
-        if (regIdxToClass(dest_reg) != MiscRegClass) {
-            // Get the physical register index of the i'th destination register.
-            dest_reg = dyn_inst->renamedDestRegIdx(dest_idx);
-            if (dest_reg != TheISA::ZeroReg) {
-                DPRINTFR(ElasticTrace, "[sn:%lli] Update map for dest reg %i\n",
-                            seq_num, dest_reg);
-                physRegDepMap[dest_reg] = seq_num;
-            }
+        RegId dest_reg = dyn_inst->destRegIdx(dest_idx);
+        if (dest_reg.isRenameable() &&
+            !dest_reg.isZeroReg()) {
+            // Get the physical register index of the i'th destination
+            // register.
+            PhysRegIndex phys_dest_reg = dyn_inst->renamedDestRegIdx(dest_idx);
+            DPRINTFR(ElasticTrace, "[sn:%lli] Update map for dest reg %i\n",
+                    seq_num, dest_reg.regIdx);
+            physRegDepMap[phys_dest_reg] = seq_num;
         }
     }
     maxPhysRegDepMapSize = std::max(physRegDepMap.size(),
diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh
index f8becc114..c0483d445 100644
--- a/src/cpu/o3/rename.hh
+++ b/src/cpu/o3/rename.hh
@@ -85,9 +85,6 @@ class DefaultRename
     typedef typename CPUPol::IEW IEW;
     typedef typename CPUPol::Commit Commit;
 
-    // Typedefs from the ISA.
-    typedef TheISA::RegIndex RegIndex;
-
     // A deque is used to queue the instructions. Barrier insts must
     // be added to the front of the queue, which is the only reason for
     // using a deque instead of a queue. (Most other stages use a
@@ -301,7 +298,7 @@ class DefaultRename
      * register for that arch. register, and the new physical register.
      */
     struct RenameHistory {
-        RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
+        RenameHistory(InstSeqNum _instSeqNum, RegId _archReg,
                       PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
             : instSeqNum(_instSeqNum), archReg(_archReg),
               newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
@@ -311,7 +308,7 @@ class DefaultRename
         /** The sequence number of the instruction that renamed. */
         InstSeqNum instSeqNum;
         /** The architectural register index that was renamed. */
-        RegIndex archReg;
+        RegId archReg;
         /** The new physical register that the arch. register is renamed to. */
         PhysRegIndex newPhysReg;
         /** The old physical register that the arch. register was renamed to. */
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 00179faae..e675efcd5 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -1011,42 +1011,41 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
     // Get the architectual register numbers from the source and
     // operands, and redirect them to the right physical register.
     for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
-        RegIndex src_reg = inst->srcRegIdx(src_idx);
-        RegIndex rel_src_reg;
-        RegIndex flat_rel_src_reg;
+        RegId src_reg = inst->srcRegIdx(src_idx);
+        RegIndex flat_src_reg;
         PhysRegIndex renamed_reg;
 
-        switch (regIdxToClass(src_reg, &rel_src_reg)) {
+        switch (src_reg.regClass) {
           case IntRegClass:
-            flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg);
-            renamed_reg = map->lookupInt(flat_rel_src_reg);
+            flat_src_reg = tc->flattenIntIndex(src_reg.regIdx);
+            renamed_reg = map->lookupInt(flat_src_reg);
             intRenameLookups++;
             break;
 
           case FloatRegClass:
-            flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg);
-            renamed_reg = map->lookupFloat(flat_rel_src_reg);
+            flat_src_reg = tc->flattenFloatIndex(src_reg.regIdx);
+            renamed_reg = map->lookupFloat(flat_src_reg);
             fpRenameLookups++;
             break;
 
           case CCRegClass:
-            flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg);
-            renamed_reg = map->lookupCC(flat_rel_src_reg);
+            flat_src_reg = tc->flattenCCIndex(src_reg.regIdx);
+            renamed_reg = map->lookupCC(flat_src_reg);
             break;
 
           case MiscRegClass:
             // misc regs don't get flattened
-            flat_rel_src_reg = rel_src_reg;
-            renamed_reg = map->lookupMisc(flat_rel_src_reg);
+            flat_src_reg = src_reg.regIdx;
+            renamed_reg = map->lookupMisc(flat_src_reg);
             break;
 
           default:
-            panic("Reg index is out of bound: %d.", src_reg);
+            panic("Invalid register class: %d.", src_reg.regClass);
         }
 
         DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), "
-                "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)],
-                (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg);
+                "got phys reg %i\n", tid, RegClassStrings[src_reg.regClass],
+                (int)src_reg.regIdx, (int)flat_src_reg, (int)renamed_reg);
 
         inst->renameSrcReg(src_idx, renamed_reg);
 
@@ -1075,49 +1074,45 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
 
     // Rename the destination registers.
     for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
-        RegIndex dest_reg = inst->destRegIdx(dest_idx);
-        RegIndex rel_dest_reg;
-        RegIndex flat_rel_dest_reg;
-        RegIndex flat_uni_dest_reg;
+        RegId dest_reg = inst->destRegIdx(dest_idx);
+        RegIndex flat_dest_reg;
         typename RenameMap::RenameInfo rename_result;
 
-        switch (regIdxToClass(dest_reg, &rel_dest_reg)) {
+        switch (dest_reg.regClass) {
           case IntRegClass:
-            flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg);
-            rename_result = map->renameInt(flat_rel_dest_reg);
-            flat_uni_dest_reg = flat_rel_dest_reg;  // 1:1 mapping
+            flat_dest_reg = tc->flattenIntIndex(dest_reg.regIdx);
+            rename_result = map->renameInt(flat_dest_reg);
             break;
 
           case FloatRegClass:
-            flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg);
-            rename_result = map->renameFloat(flat_rel_dest_reg);
-            flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base;
+            flat_dest_reg = tc->flattenFloatIndex(dest_reg.regIdx);
+            rename_result = map->renameFloat(flat_dest_reg);
             break;
 
           case CCRegClass:
-            flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg);
-            rename_result = map->renameCC(flat_rel_dest_reg);
-            flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base;
+            flat_dest_reg = tc->flattenCCIndex(dest_reg.regIdx);
+            rename_result = map->renameCC(flat_dest_reg);
             break;
 
           case MiscRegClass:
             // misc regs don't get flattened
-            flat_rel_dest_reg = rel_dest_reg;
-            rename_result = map->renameMisc(flat_rel_dest_reg);
-            flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base;
+            flat_dest_reg = dest_reg.regIdx;
+            rename_result = map->renameMisc(dest_reg.regIdx);
             break;
 
           default:
-            panic("Reg index is out of bound: %d.", dest_reg);
+            panic("Invalid register class: %d.", dest_reg.regClass);
         }
 
+        RegId flat_uni_dest_reg(dest_reg.regClass, flat_dest_reg);
+
         inst->flattenDestReg(dest_idx, flat_uni_dest_reg);
 
         // Mark Scoreboard entry as not ready
         scoreboard->unsetReg(rename_result.first);
 
         DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
-                "reg %i.\n", tid, (int)flat_rel_dest_reg,
+                "reg %i.\n", tid, (int)flat_dest_reg,
                 (int)rename_result.first);
 
         // Record the rename information so that a history can be kept.
@@ -1431,8 +1426,10 @@ DefaultRename<Impl>::dumpHistory()
         buf_it = historyBuffer[tid].begin();
 
         while (buf_it != historyBuffer[tid].end()) {
-            cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
-                    "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
+            cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg: %i Old phys "
+                    "reg: %i\n", (*buf_it).instSeqNum,
+                    RegClassStrings[(*buf_it).archReg.regClass],
+                    (*buf_it).archReg.regIdx,
                     (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
 
             buf_it++;
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index 18c20cf8c..6307b58de 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -104,79 +104,73 @@ UnifiedRenameMap::init(PhysRegFile *_regFile,
 
 
 UnifiedRenameMap::RenameInfo
-UnifiedRenameMap::rename(RegIndex arch_reg)
+UnifiedRenameMap::rename(RegId arch_reg)
 {
-    RegIndex rel_arch_reg;
-
-    switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
+    switch (arch_reg.regClass) {
       case IntRegClass:
-        return renameInt(rel_arch_reg);
+        return renameInt(arch_reg.regIdx);
 
       case FloatRegClass:
-        return renameFloat(rel_arch_reg);
+        return renameFloat(arch_reg.regIdx);
 
       case CCRegClass:
-        return renameCC(rel_arch_reg);
+        return renameCC(arch_reg.regIdx);
 
       case MiscRegClass:
-        return renameMisc(rel_arch_reg);
+        return renameMisc(arch_reg.regIdx);
 
       default:
         panic("rename rename(): unknown reg class %s\n",
-              RegClassStrings[regIdxToClass(arch_reg)]);
+              RegClassStrings[arch_reg.regClass]);
     }
 }
 
 
 PhysRegIndex
-UnifiedRenameMap::lookup(RegIndex arch_reg) const
+UnifiedRenameMap::lookup(RegId arch_reg) const
 {
-    RegIndex rel_arch_reg;
-
-    switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
+    switch (arch_reg.regClass) {
       case IntRegClass:
-        return lookupInt(rel_arch_reg);
+        return lookupInt(arch_reg.regIdx);
 
       case FloatRegClass:
-        return lookupFloat(rel_arch_reg);
+        return lookupFloat(arch_reg.regIdx);
 
       case CCRegClass:
-        return lookupCC(rel_arch_reg);
+        return lookupCC(arch_reg.regIdx);
 
       case MiscRegClass:
-        return lookupMisc(rel_arch_reg);
+        return lookupMisc(arch_reg.regIdx);
 
       default:
         panic("rename lookup(): unknown reg class %s\n",
-              RegClassStrings[regIdxToClass(arch_reg)]);
+              RegClassStrings[arch_reg.regClass]);
     }
 }
 
 void
-UnifiedRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
+UnifiedRenameMap::setEntry(RegId arch_reg, PhysRegIndex phys_reg)
 {
-    RegIndex rel_arch_reg;
-
-    switch (regIdxToClass(arch_reg, &rel_arch_reg)) {
+    switch (arch_reg.regClass) {
       case IntRegClass:
-        return setIntEntry(rel_arch_reg, phys_reg);
+        return setIntEntry(arch_reg.regIdx, phys_reg);
 
       case FloatRegClass:
-        return setFloatEntry(rel_arch_reg, phys_reg);
+        return setFloatEntry(arch_reg.regIdx, phys_reg);
 
       case CCRegClass:
-        return setCCEntry(rel_arch_reg, phys_reg);
+        return setCCEntry(arch_reg.regIdx, phys_reg);
 
       case MiscRegClass:
         // Misc registers do not actually rename, so don't change
         // their mappings.  We end up here when a commit or squash
         // tries to update or undo a hardwired misc reg nmapping,
         // which should always be setting it to what it already is.
-        assert(phys_reg == lookupMisc(rel_arch_reg));
+        assert(phys_reg == lookupMisc(arch_reg.regIdx));
         return;
 
       default:
         panic("rename setEntry(): unknown reg class %s\n",
-              RegClassStrings[regIdxToClass(arch_reg)]);
+              RegClassStrings[arch_reg.regClass]);
     }
 }
diff --git a/src/cpu/o3/rename_map.hh b/src/cpu/o3/rename_map.hh
index 9d91f232e..2cce29913 100644
--- a/src/cpu/o3/rename_map.hh
+++ b/src/cpu/o3/rename_map.hh
@@ -68,10 +68,6 @@
  */
 class SimpleRenameMap
 {
-  public:
-
-    typedef TheISA::RegIndex RegIndex;
-
   private:
 
     /** The acutal arch-to-phys register map */
@@ -152,9 +148,9 @@ class SimpleRenameMap
 /**
  * Unified register rename map for all classes of registers.  Wraps a
  * set of class-specific rename maps.  Methods that do not specify a
- * register class (e.g., rename()) take unified register indices,
+ * register class (e.g., rename()) take register ids,
  * while methods that do specify a register class (e.g., renameInt())
- * take relative register indices.  See http://gem5.org/Register_Indexing.
+ * take register indices.
  */
 class UnifiedRenameMap
 {
@@ -179,7 +175,6 @@ class UnifiedRenameMap
     SimpleRenameMap ccMap;
 
   public:
-    typedef TheISA::RegIndex RegIndex;
 
     typedef SimpleRenameMap::RenameInfo RenameInfo;
 
@@ -197,17 +192,17 @@ class UnifiedRenameMap
 
     /**
      * Tell rename map to get a new free physical register to remap
-     * the specified architectural register.  This version takes a
-     * unified flattened architectural register index and calls the
+     * the specified architectural register. This version takes a
+     * flattened architectural register id and calls the
      * appropriate class-specific rename table.
-     * @param arch_reg The unified architectural register index to remap.
+     * @param arch_reg The architectural register index to remap.
      * @return A RenameInfo pair indicating both the new and previous
      * physical registers.
      */
-    RenameInfo rename(RegIndex arch_reg);
+    RenameInfo rename(RegId arch_reg);
 
     /**
-     * Perform rename() on an integer register, given a relative
+     * Perform rename() on an integer register, given a
      * integer register index.
      */
     RenameInfo renameInt(RegIndex rel_arch_reg)
@@ -218,7 +213,7 @@ class UnifiedRenameMap
     }
 
     /**
-     * Perform rename() on a floating-point register, given a relative
+     * Perform rename() on a floating-point register, given a
      * floating-point register index.
      */
     RenameInfo renameFloat(RegIndex rel_arch_reg)
@@ -229,7 +224,7 @@ class UnifiedRenameMap
     }
 
     /**
-     * Perform rename() on a condition-code register, given a relative
+     * Perform rename() on a condition-code register, given a
      * condition-code register index.
      */
     RenameInfo renameCC(RegIndex rel_arch_reg)
@@ -240,7 +235,7 @@ class UnifiedRenameMap
     }
 
     /**
-     * Perform rename() on a misc register, given a relative
+     * Perform rename() on a misc register, given a
      * misc register index.
      */
     RenameInfo renameMisc(RegIndex rel_arch_reg)
@@ -256,15 +251,15 @@ class UnifiedRenameMap
 
     /**
      * Look up the physical register mapped to an architectural register.
-     * This version takes a unified flattened architectural register index
+     * This version takes a flattened architectural register id
      * and calls the appropriate class-specific rename table.
-     * @param arch_reg The unified architectural register to look up.
+     * @param arch_reg The architectural register to look up.
      * @return The physical register it is currently mapped to.
      */
-    PhysRegIndex lookup(RegIndex arch_reg) const;
+    PhysRegIndex lookup(RegId arch_reg) const;
 
     /**
-     * Perform lookup() on an integer register, given a relative
+     * Perform lookup() on an integer register, given a
      * integer register index.
      */
     PhysRegIndex lookupInt(RegIndex rel_arch_reg) const
@@ -275,7 +270,7 @@ class UnifiedRenameMap
     }
 
     /**
-     * Perform lookup() on a floating-point register, given a relative
+     * Perform lookup() on a floating-point register, given a
      * floating-point register index.
      */
     PhysRegIndex lookupFloat(RegIndex rel_arch_reg) const
@@ -286,7 +281,7 @@ class UnifiedRenameMap
     }
 
     /**
-     * Perform lookup() on a condition-code register, given a relative
+     * Perform lookup() on a condition-code register, given a
      * condition-code register index.
      */
     PhysRegIndex lookupCC(RegIndex rel_arch_reg) const
@@ -311,15 +306,15 @@ class UnifiedRenameMap
     /**
      * Update rename map with a specific mapping.  Generally used to
      * roll back to old mappings on a squash.  This version takes a
-     * unified flattened architectural register index and calls the
+     * flattened architectural register id and calls the
      * appropriate class-specific rename table.
-     * @param arch_reg The unified architectural register to remap.
+     * @param arch_reg The architectural register to remap.
      * @param phys_reg The physical register to remap it to.
      */
-    void setEntry(RegIndex arch_reg, PhysRegIndex phys_reg);
+    void setEntry(RegId arch_reg, PhysRegIndex phys_reg);
 
     /**
-     * Perform setEntry() on an integer register, given a relative
+     * Perform setEntry() on an integer register, given a
      * integer register index.
      */
     void setIntEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
@@ -329,7 +324,7 @@ class UnifiedRenameMap
     }
 
     /**
-     * Perform setEntry() on a floating-point register, given a relative
+     * Perform setEntry() on a floating-point register, given a
      * floating-point register index.
      */
     void setFloatEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
@@ -339,7 +334,7 @@ class UnifiedRenameMap
     }
 
     /**
-     * Perform setEntry() on a condition-code register, given a relative
+     * Perform setEntry() on a condition-code register, given a
      * condition-code register index.
      */
     void setCCEntry(RegIndex arch_reg, PhysRegIndex phys_reg)
diff --git a/src/cpu/o3/rob.hh b/src/cpu/o3/rob.hh
index b5651de11..1c3cc2815 100644
--- a/src/cpu/o3/rob.hh
+++ b/src/cpu/o3/rob.hh
@@ -60,8 +60,6 @@ struct DerivO3CPUParams;
 template <class Impl>
 class ROB
 {
-  protected:
-    typedef TheISA::RegIndex RegIndex;
   public:
     //Typedefs from the Impl.
     typedef typename Impl::O3CPU O3CPU;