diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-15 14:22:42 -0400 |
---|---|---|
committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-15 14:22:42 -0400 |
commit | 7aa423acad07f05ee547117406a72a5c1b4f6015 (patch) | |
tree | a4a9f24bb94a743b0316ea2a907d07daddc4ffc3 /src/cpu/o3 | |
parent | 4f5775df64b1b16ef4a3a02b12e4ac8a6370baed (diff) | |
download | gem5-7aa423acad07f05ee547117406a72a5c1b4f6015.tar.xz |
cpu: clean up architectural register classification
Move from a poorly documented scheme where the mapping
of unified architectural register indices to register
classes is hardcoded all over to one where there's an
enum for the register classes and a function that
encapsulates the mapping.
Diffstat (limited to 'src/cpu/o3')
-rw-r--r-- | src/cpu/o3/dyn_inst.hh | 22 | ||||
-rw-r--r-- | src/cpu/o3/rename_impl.hh | 34 |
2 files changed, 42 insertions, 14 deletions
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 082c1f5d4..ece42b81a 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2010 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * * The license below extends only to copyright in the software and shall @@ -49,6 +50,7 @@ #include "cpu/o3/isa_specific.hh" #include "cpu/base_dyn_inst.hh" #include "cpu/inst_seq.hh" +#include "cpu/reg_class.hh" class Packet; @@ -209,11 +211,21 @@ class BaseO3DynInst : public BaseDynInst<Impl> for (int idx = 0; idx < this->numDestRegs(); idx++) { PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx); - TheISA::RegIndex original_dest_reg = this->staticInst->destRegIdx(idx); - if (original_dest_reg < TheISA::FP_Base_DepTag) - this->setIntRegOperand(this->staticInst.get(), idx, this->cpu->readIntReg(prev_phys_reg)); - else if (original_dest_reg < TheISA::Ctrl_Base_DepTag) - this->setFloatRegOperandBits(this->staticInst.get(), idx, this->cpu->readFloatRegBits(prev_phys_reg)); + TheISA::RegIndex original_dest_reg = + this->staticInst->destRegIdx(idx); + switch (regIdxToClass(original_dest_reg)) { + case IntRegClass: + this->setIntRegOperand(this->staticInst.get(), idx, + this->cpu->readIntReg(prev_phys_reg)); + break; + case FloatRegClass: + this->setFloatRegOperandBits(this->staticInst.get(), idx, + this->cpu->readFloatRegBits(prev_phys_reg)); + break; + case MiscRegClass: + // no need to forward misc reg values + break; + } } } /** Calls hardware return from error interrupt. */ diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 341ba8804..6e564abab 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2010-2012 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -47,6 +48,7 @@ #include "arch/registers.hh" #include "config/the_isa.hh" #include "cpu/o3/rename.hh" +#include "cpu/reg_class.hh" #include "debug/Activity.hh" #include "debug/Rename.hh" #include "debug/O3PipeView.hh" @@ -948,22 +950,29 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { RegIndex src_reg = inst->srcRegIdx(src_idx); RegIndex flat_src_reg = src_reg; - if (src_reg < TheISA::FP_Base_DepTag) { + switch (regIdxToClass(src_reg)) { + case IntRegClass: flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg); DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); - } else if (src_reg < TheISA::Ctrl_Base_DepTag) { + break; + + case FloatRegClass: src_reg = src_reg - TheISA::FP_Base_DepTag; flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); flat_src_reg += TheISA::NumIntRegs; - } else if (src_reg < TheISA::Max_DepTag) { + break; + + case MiscRegClass: flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag + TheISA::NumFloatRegs + TheISA::NumIntRegs; DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg); - } else { + break; + + default: panic("Reg index is out of bound: %d.", src_reg); } @@ -1005,25 +1014,32 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { RegIndex dest_reg = inst->destRegIdx(dest_idx); RegIndex flat_dest_reg = dest_reg; - if (dest_reg < TheISA::FP_Base_DepTag) { + switch (regIdxToClass(dest_reg)) { + case IntRegClass: // Integer registers are flattened. flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg); DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); - } else if (dest_reg < TheISA::Ctrl_Base_DepTag) { + break; + + case FloatRegClass: dest_reg = dest_reg - TheISA::FP_Base_DepTag; flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg); DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); flat_dest_reg += TheISA::NumIntRegs; - } else if (dest_reg < TheISA::Max_DepTag) { + break; + + case MiscRegClass: // Floating point and Miscellaneous registers need their indexes // adjusted to account for the expanded number of flattened int regs. flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag + TheISA::NumIntRegs + TheISA::NumFloatRegs; DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg); - } else { + break; + + default: panic("Reg index is out of bound: %d.", dest_reg); } @@ -1034,7 +1050,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) rename_result = renameMap[tid]->rename(flat_dest_reg); //Mark Scoreboard entry as not ready - if (dest_reg < TheISA::Ctrl_Base_DepTag) + if (regIdxToClass(dest_reg) != MiscRegClass) scoreboard->unsetReg(rename_result.first); DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " |