cpu: dev: sim: gpu-compute: Banish some ISA specific register types.

These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are
some remaining types, specifically the vector registers and the CCReg.
I'm less familiar with these new types of registers, and so will look
at getting rid of them at some later time.

Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
Reviewed-on: https://gem5-review.googlesource.com/c/13624
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 files changed, 129 insertions, 98 deletions

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 8f399e9f5..c65e509f9 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1244,14 +1244,14 @@ FullO3CPU<Impl>::verifyMemoryMode() const
 }
 
 template <class Impl>
-TheISA::MiscReg
+RegVal
 FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
 {
     return this->isa[tid]->readMiscRegNoEffect(misc_reg);
 }
 
 template <class Impl>
-TheISA::MiscReg
+RegVal
 FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
 {
     miscRegfileReads++;
@@ -1261,7 +1261,7 @@ FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
 template <class Impl>
 void
 FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
-        const TheISA::MiscReg &val, ThreadID tid)
+        const RegVal &val, ThreadID tid)
 {
     this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
 }
@@ -1269,14 +1269,14 @@ FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
 template <class Impl>
 void
 FullO3CPU<Impl>::setMiscReg(int misc_reg,
-        const TheISA::MiscReg &val, ThreadID tid)
+        const RegVal &val, ThreadID tid)
 {
     miscRegfileWrites++;
     this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
 }
 
 template <class Impl>
-uint64_t
+RegVal
 FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
 {
     intRegfileReads++;
@@ -1284,7 +1284,7 @@ FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
 }
 
 template <class Impl>
-FloatRegBits
+RegVal
 FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
 {
     fpRegfileReads++;
@@ -1327,7 +1327,7 @@ FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
+FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val)
 {
     intRegfileWrites++;
     regFile.setIntReg(phys_reg, val);
@@ -1335,7 +1335,7 @@ FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
+FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val)
 {
     fpRegfileWrites++;
     regFile.setFloatRegBits(phys_reg, val);
@@ -1366,7 +1366,7 @@ FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
 }
 
 template <class Impl>
-uint64_t
+RegVal
 FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
 {
     intRegfileReads++;
@@ -1377,7 +1377,7 @@ FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
 }
 
 template <class Impl>
-uint64_t
+RegVal
 FullO3CPU<Impl>::readArchFloatRegBits(int reg_idx, ThreadID tid)
 {
     fpRegfileReads++;
@@ -1430,7 +1430,7 @@ FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
+FullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
 {
     intRegfileWrites++;
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
@@ -1441,7 +1441,7 @@ FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, uint64_t val, ThreadID tid)
+FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid)
 {
     fpRegfileWrites++;
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 4c4677615..431eb0f2f 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -382,26 +382,24 @@ class FullO3CPU : public BaseO3CPU
     /** Register accessors.  Index refers to the physical register index. */
 
     /** Reads a miscellaneous register. */
-    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
+    RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
 
     /** Reads a misc. register, including any side effects the read
      * might have as defined by the architecture.
      */
-    TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
+    RegVal readMiscReg(int misc_reg, ThreadID tid);
 
     /** Sets a miscellaneous register. */
-    void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
-            ThreadID tid);
+    void setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid);
 
     /** Sets a misc. register, including any side effects the write
      * might have as defined by the architecture.
      */
-    void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
-            ThreadID tid);
+    void setMiscReg(int misc_reg, const RegVal &val, ThreadID tid);
 
-    uint64_t readIntReg(PhysRegIdPtr phys_reg);
+    RegVal readIntReg(PhysRegIdPtr phys_reg);
 
-    TheISA::FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg);
+    RegVal readFloatRegBits(PhysRegIdPtr phys_reg);
 
     const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
 
@@ -445,9 +443,9 @@ class FullO3CPU : public BaseO3CPU
 
     TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);
 
-    void setIntReg(PhysRegIdPtr phys_reg, uint64_t val);
+    void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
 
-    void setFloatRegBits(PhysRegIdPtr phys_reg, TheISA::FloatRegBits val);
+    void setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val);
 
     void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
 
@@ -455,9 +453,9 @@ class FullO3CPU : public BaseO3CPU
 
     void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);
 
-    uint64_t readArchIntReg(int reg_idx, ThreadID tid);
+    RegVal readArchIntReg(int reg_idx, ThreadID tid);
 
-    uint64_t readArchFloatRegBits(int reg_idx, ThreadID tid);
+    RegVal readArchFloatRegBits(int reg_idx, ThreadID tid);
 
     const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
     /** Read architectural vector register for modification. */
@@ -494,9 +492,9 @@ class FullO3CPU : public BaseO3CPU
      * architected register first, then accesses that physical
      * register.
      */
-    void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
+    void setArchIntReg(int reg_idx, RegVal val, ThreadID tid);
 
-    void setArchFloatRegBits(int reg_idx, uint64_t val, ThreadID tid);
+    void setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid);
 
     void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
 
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index d4fbc78f9..9054b2089 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -66,17 +66,11 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     /** Binary machine instruction type. */
     typedef TheISA::MachInst MachInst;
     /** Register types. */
-    typedef TheISA::IntReg   IntReg;
-    typedef TheISA::FloatReg FloatReg;
-    typedef TheISA::FloatRegBits FloatRegBits;
     typedef TheISA::CCReg   CCReg;
     using VecRegContainer = TheISA::VecRegContainer;
     using VecElem = TheISA::VecElem;
     static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
 
-    /** Misc register type. */
-    typedef TheISA::MiscReg  MiscReg;
-
     enum {
         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
         MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
@@ -114,7 +108,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     using BaseDynInst<Impl>::_destRegIdx;
 
     /** Values to be written to the destination misc. registers. */
-    std::array<MiscReg, TheISA::MaxMiscDestRegs> _destMiscRegVal;
+    std::array<RegVal, TheISA::MaxMiscDestRegs> _destMiscRegVal;
 
     /** Indexes of the destination misc. registers. They are needed to defer
      * the write accesses to the misc. registers until the commit stage, when
@@ -142,7 +136,8 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     /** Reads a misc. register, including any side-effects the read
      * might have as defined by the architecture.
      */
-    MiscReg readMiscReg(int misc_reg)
+    RegVal
+    readMiscReg(int misc_reg)
     {
         return this->cpu->readMiscReg(misc_reg, this->threadNumber);
     }
@@ -150,7 +145,8 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     /** Sets a misc. register, including any side-effects the write
      * might have as defined by the architecture.
      */
-    void setMiscReg(int misc_reg, const MiscReg &val)
+    void
+    setMiscReg(int misc_reg, const RegVal &val)
     {
         /** Writes to misc. registers are recorded and deferred until the
          * commit stage, when updateMiscRegs() is called. First, check if
@@ -174,7 +170,8 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     /** Reads a misc. register, including any side-effects the read
      * might have as defined by the architecture.
      */
-    TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
+    RegVal
+    readMiscRegOperand(const StaticInst *si, int idx)
     {
         const RegId& reg = si->srcRegIdx(idx);
         assert(reg.isMiscReg());
@@ -184,8 +181,8 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     /** Sets a misc. register, including any side-effects the write
      * might have as defined by the architecture.
      */
-    void setMiscRegOperand(const StaticInst *si, int idx,
-                                     const MiscReg &val)
+    void
+    setMiscRegOperand(const StaticInst *si, int idx, const RegVal &val)
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isMiscReg());
@@ -193,7 +190,8 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     }
 
     /** Called at the commit stage to update the misc. registers. */
-    void updateMiscRegs()
+    void
+    updateMiscRegs()
     {
         // @todo: Pretty convoluted way to avoid squashing from happening when
         // using the TC during an instruction's execution (specifically for
@@ -268,12 +266,14 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     // storage (which is pretty hard to imagine they would have reason
     // to do).
 
-    IntReg readIntRegOperand(const StaticInst *si, int idx)
+    RegVal
+    readIntRegOperand(const StaticInst *si, int idx)
     {
         return this->cpu->readIntReg(this->_srcRegIdx[idx]);
     }
 
-    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
+    RegVal
+    readFloatRegOperandBits(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
     }
@@ -369,14 +369,15 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     /** @todo: Make results into arrays so they can handle multiple dest
      *  registers.
      */
-    void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
+    void
+    setIntRegOperand(const StaticInst *si, int idx, RegVal val)
     {
         this->cpu->setIntReg(this->_destRegIdx[idx], val);
         BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
     }
 
-    void setFloatRegOperandBits(const StaticInst *si, int idx,
-                                FloatRegBits val)
+    void
+    setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
     {
         this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
         BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
@@ -405,13 +406,15 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     }
 
 #if THE_ISA == MIPS_ISA
-    MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid)
+    RegVal
+    readRegOtherThread(const RegId& misc_reg, ThreadID tid)
     {
         panic("MIPS MT not defined for O3 CPU.\n");
         return 0;
     }
 
-    void setRegOtherThread(const RegId& misc_reg, MiscReg val, ThreadID tid)
+    void
+    setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
     {
         panic("MIPS MT not defined for O3 CPU.\n");
     }
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 354fe2bc5..9d9113240 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -65,9 +65,6 @@ class PhysRegFile
 {
   private:
 
-    typedef TheISA::IntReg IntReg;
-    typedef TheISA::FloatReg FloatReg;
-    typedef TheISA::FloatRegBits FloatRegBits;
     typedef TheISA::CCReg CCReg;
     using VecElem = TheISA::VecElem;
     using VecRegContainer = TheISA::VecRegContainer;
@@ -80,11 +77,11 @@ class PhysRegFile
     static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
 
     /** Integer register file. */
-    std::vector<IntReg> intRegFile;
+    std::vector<RegVal> intRegFile;
     std::vector<PhysRegId> intRegIds;
 
     /** Floating point register file. */
-    std::vector<FloatRegBits> floatRegFile;
+    std::vector<RegVal> floatRegFile;
     std::vector<PhysRegId> floatRegIds;
 
     /** Vector register file. */
@@ -173,7 +170,8 @@ class PhysRegFile
     }
 
     /** Reads an integer register. */
-    uint64_t readIntReg(PhysRegIdPtr phys_reg) const
+    RegVal
+    readIntReg(PhysRegIdPtr phys_reg) const
     {
         assert(phys_reg->isIntPhysReg());
 
@@ -182,21 +180,22 @@ class PhysRegFile
         return intRegFile[phys_reg->index()];
     }
 
-    FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg) const
+    RegVal
+    readFloatRegBits(PhysRegIdPtr phys_reg) const
     {
         assert(phys_reg->isFloatPhysReg());
 
-        FloatRegBits floatRegBits = floatRegFile[phys_reg->index()];
+        RegVal floatRegBits = floatRegFile[phys_reg->index()];
 
         DPRINTF(IEW, "RegFile: Access to float register %i as int, "
-                "has data %#x\n", phys_reg->index(),
-                (uint64_t)floatRegBits);
+                "has data %#x\n", phys_reg->index(), floatRegBits);
 
         return floatRegBits;
     }
 
     /** Reads a vector register. */
-    const VecRegContainer& readVecReg(PhysRegIdPtr phys_reg) const
+    const VecRegContainer &
+    readVecReg(PhysRegIdPtr phys_reg) const
     {
         assert(phys_reg->isVectorPhysReg());
 
@@ -208,7 +207,8 @@ class PhysRegFile
     }
 
     /** Reads a vector register for modification. */
-    VecRegContainer& getWritableVecReg(PhysRegIdPtr phys_reg)
+    VecRegContainer &
+    getWritableVecReg(PhysRegIdPtr phys_reg)
     {
         /* const_cast for not duplicating code above. */
         return const_cast<VecRegContainer&>(readVecReg(phys_reg));
@@ -245,7 +245,8 @@ class PhysRegFile
     }
 
     /** Reads a vector element. */
-    const VecElem& readVecElem(PhysRegIdPtr phys_reg) const
+    const VecElem &
+    readVecElem(PhysRegIdPtr phys_reg) const
     {
         assert(phys_reg->isVectorPhysElem());
         auto ret = vectorRegFile[phys_reg->index()].as<VecElem>();
@@ -258,7 +259,8 @@ class PhysRegFile
     }
 
     /** Reads a condition-code register. */
-    CCReg readCCReg(PhysRegIdPtr phys_reg)
+    CCReg
+    readCCReg(PhysRegIdPtr phys_reg)
     {
         assert(phys_reg->isCCPhysReg());
 
@@ -270,7 +272,8 @@ class PhysRegFile
     }
 
     /** Sets an integer register to the given value. */
-    void setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
+    void
+    setIntReg(PhysRegIdPtr phys_reg, RegVal val)
     {
         assert(phys_reg->isIntPhysReg());
 
@@ -281,7 +284,8 @@ class PhysRegFile
             intRegFile[phys_reg->index()] = val;
     }
 
-    void setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
+    void
+    setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val)
     {
         assert(phys_reg->isFloatPhysReg());
 
@@ -293,7 +297,8 @@ class PhysRegFile
     }
 
     /** Sets a vector register to the given value. */
-    void setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
+    void
+    setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
     {
         assert(phys_reg->isVectorPhysReg());
 
@@ -304,7 +309,8 @@ class PhysRegFile
     }
 
     /** Sets a vector register to the given value. */
-    void setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
+    void
+    setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
     {
         assert(phys_reg->isVectorPhysElem());
 
@@ -316,7 +322,8 @@ class PhysRegFile
     }
 
     /** Sets a condition-code register to the given value. */
-    void setCCReg(PhysRegIdPtr phys_reg, CCReg val)
+    void
+    setCCReg(PhysRegIdPtr phys_reg, CCReg val)
     {
         assert(phys_reg->isCCPhysReg());
 
@@ -338,12 +345,12 @@ class PhysRegFile
      */
     IdRange getRegIds(RegClass cls);
 
-     /**
-      * Get the true physical register id.
-      * As many parts work with PhysRegIdPtr, we need to be able to produce
-      * the pointer out of just class and register idx.
-      */
-     PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
+    /**
+     * Get the true physical register id.
+     * As many parts work with PhysRegIdPtr, we need to be able to produce
+     * the pointer out of just class and register idx.
+     */
+    PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
 };
 
 
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 1fbf565f5..510e96432 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -175,28 +175,38 @@ class O3ThreadContext : public ThreadContext
     virtual void clearArchRegs();
 
     /** Reads an integer register. */
-    virtual uint64_t readReg(int reg_idx) {
+    virtual RegVal
+    readReg(int reg_idx)
+    {
         return readIntRegFlat(flattenRegId(RegId(IntRegClass,
                                                  reg_idx)).index());
     }
-    virtual uint64_t readIntReg(int reg_idx) {
+    virtual RegVal
+    readIntReg(int reg_idx)
+    {
         return readIntRegFlat(flattenRegId(RegId(IntRegClass,
                                                  reg_idx)).index());
     }
 
-    virtual FloatRegBits readFloatRegBits(int reg_idx) {
+    virtual RegVal
+    readFloatRegBits(int reg_idx)
+    {
         return readFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass,
                                                  reg_idx)).index());
     }
 
-    virtual const VecRegContainer& readVecReg(const RegId& id) const {
+    virtual const VecRegContainer &
+    readVecReg(const RegId& id) const
+    {
         return readVecRegFlat(flattenRegId(id).index());
     }
 
     /**
      * Read vector register operand for modification, hierarchical indexing.
      */
-    virtual VecRegContainer& getWritableVecReg(const RegId& id) {
+    virtual VecRegContainer &
+    getWritableVecReg(const RegId& id)
+    {
         return getWritableVecRegFlat(flattenRegId(id).index());
     }
 
@@ -259,24 +269,34 @@ class O3ThreadContext : public ThreadContext
     }
 
     /** Sets an integer register to a value. */
-    virtual void setIntReg(int reg_idx, uint64_t val) {
+    virtual void
+    setIntReg(int reg_idx, RegVal val)
+    {
         setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val);
     }
 
-    virtual void setFloatRegBits(int reg_idx, FloatRegBits val) {
+    virtual void
+    setFloatRegBits(int reg_idx, RegVal val)
+    {
         setFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass,
                                                reg_idx)).index(), val);
     }
 
-    virtual void setVecReg(const RegId& reg, const VecRegContainer& val) {
+    virtual void
+    setVecReg(const RegId& reg, const VecRegContainer& val)
+    {
         setVecRegFlat(flattenRegId(reg).index(), val);
     }
 
-    virtual void setVecElem(const RegId& reg, const VecElem& val) {
+    virtual void
+    setVecElem(const RegId& reg, const VecElem& val)
+    {
         setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
     }
 
-    virtual void setCCReg(int reg_idx, CCReg val) {
+    virtual void
+    setCCReg(int reg_idx, CCReg val)
+    {
         setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
     }
 
@@ -302,20 +322,20 @@ class O3ThreadContext : public ThreadContext
     { return cpu->microPC(thread->threadId()); }
 
     /** Reads a miscellaneous register. */
-    virtual MiscReg readMiscRegNoEffect(int misc_reg) const
+    virtual RegVal readMiscRegNoEffect(int misc_reg) const
     { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
 
     /** Reads a misc. register, including any side-effects the
      * read might have as defined by the architecture. */
-    virtual MiscReg readMiscReg(int misc_reg)
+    virtual RegVal readMiscReg(int misc_reg)
     { return cpu->readMiscReg(misc_reg, thread->threadId()); }
 
     /** Sets a misc. register. */
-    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
+    virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val);
 
     /** Sets a misc. register, including any side-effects the
      * write might have as defined by the architecture. */
-    virtual void setMiscReg(int misc_reg, const MiscReg &val);
+    virtual void setMiscReg(int misc_reg, const RegVal &val);
 
     virtual RegId flattenRegId(const RegId& regId) const;
 
@@ -336,7 +356,8 @@ class O3ThreadContext : public ThreadContext
     virtual Counter readFuncExeInst() { return thread->funcExeInst; }
 
     /** Returns pointer to the quiesce event. */
-    virtual EndQuiesceEvent *getQuiesceEvent()
+    virtual EndQuiesceEvent *
+    getQuiesceEvent()
     {
         return this->thread->quiesceEvent;
     }
@@ -345,17 +366,18 @@ class O3ThreadContext : public ThreadContext
      * similar is currently writing to the thread context and doesn't want
      * reset all the state (see noSquashFromTC).
      */
-    inline void conditionalSquash()
+    inline void
+    conditionalSquash()
     {
         if (!thread->trapPending && !thread->noSquashFromTC)
             cpu->squashFromTC(thread->threadId());
     }
 
-    virtual uint64_t readIntRegFlat(int idx);
-    virtual void setIntRegFlat(int idx, uint64_t val);
+    virtual RegVal readIntRegFlat(int idx);
+    virtual void setIntRegFlat(int idx, RegVal val);
 
-    virtual FloatRegBits readFloatRegBitsFlat(int idx);
-    virtual void setFloatRegBitsFlat(int idx, FloatRegBits val);
+    virtual RegVal readFloatRegBitsFlat(int idx);
+    virtual void setFloatRegBitsFlat(int idx, RegVal val);
 
     virtual const VecRegContainer& readVecRegFlat(int idx) const;
     /** Read vector register operand for modification, flat indexing. */
@@ -363,7 +385,8 @@ class O3ThreadContext : public ThreadContext
     virtual void setVecRegFlat(int idx, const VecRegContainer& val);
 
     template <typename VecElem>
-    VecLaneT<VecElem, true> readVecLaneFlat(int idx, int lId) const
+    VecLaneT<VecElem, true>
+    readVecLaneFlat(int idx, int lId) const
     {
         return cpu->template readArchVecLane<VecElem>(idx, lId,
                 thread->threadId());
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index f4b5cb4f4..086d2cfeb 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -193,14 +193,14 @@ O3ThreadContext<Impl>::clearArchRegs()
 }
 
 template <class Impl>
-uint64_t
+RegVal
 O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
 {
     return cpu->readArchIntReg(reg_idx, thread->threadId());
 }
 
 template <class Impl>
-TheISA::FloatRegBits
+RegVal
 O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
 {
     return cpu->readArchFloatRegBits(reg_idx, thread->threadId());
@@ -237,7 +237,7 @@ O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
+O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, RegVal val)
 {
     cpu->setArchIntReg(reg_idx, val, thread->threadId());
 
@@ -246,7 +246,7 @@ O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
+O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, RegVal val)
 {
     cpu->setArchFloatRegBits(reg_idx, val, thread->threadId());
 
@@ -307,7 +307,7 @@ O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const RegVal &val)
 {
     cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
 
@@ -317,7 +317,7 @@ O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 #endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
 template <class Impl>
 void
-O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
+O3ThreadContext<Impl>::setMiscReg(int misc_reg, const RegVal &val)
 {
     cpu->setMiscReg(misc_reg, val, thread->threadId());