branch predictor: move out of o3 and inorder cpus

This patch moves the branch predictor files in the o3 and inorder directories
to src/cpu/pred. This allows sharing the branch predictor across different
cpu models.

This patch was originally posted by Timothy Jones in July 2010
but never made it to the repository.

--HG--
rename : src/cpu/o3/bpred_unit.cc => src/cpu/pred/bpred_unit.cc
rename : src/cpu/o3/bpred_unit.hh => src/cpu/pred/bpred_unit.hh
rename : src/cpu/o3/bpred_unit_impl.hh => src/cpu/pred/bpred_unit_impl.hh
rename : src/cpu/o3/sat_counter.hh => src/cpu/pred/sat_counter.hh

11 files changed, 14 insertions, 1061 deletions

diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 5fec3c547..4f720a8f6 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -32,6 +32,7 @@ from m5.proxy import *
 from BaseCPU import BaseCPU
 from FUPool import *
 from O3Checker import O3Checker
+from BranchPredictor import BranchPredictor
 
 class DerivO3CPU(BaseCPU):
     type = 'DerivO3CPU'
@@ -84,22 +85,6 @@ class DerivO3CPU(BaseCPU):
     backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
     forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
 
-    predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')")
-    localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
-    localCtrBits = Param.Unsigned(2, "Bits per counter")
-    localHistoryTableSize = Param.Unsigned(2048, "Size of local history table")
-    localHistoryBits = Param.Unsigned(11, "Bits for the local history")
-    globalPredictorSize = Param.Unsigned(8192, "Size of global predictor")
-    globalCtrBits = Param.Unsigned(2, "Bits per counter")
-    globalHistoryBits = Param.Unsigned(13, "Bits of history")
-    choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor")
-    choiceCtrBits = Param.Unsigned(2, "Bits of choice counters")
-
-    BTBEntries = Param.Unsigned(4096, "Number of BTB entries")
-    BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits")
-
-    RASSize = Param.Unsigned(16, "RAS size")
-
     LQEntries = Param.Unsigned(32, "Number of load queue entries")
     SQEntries = Param.Unsigned(32, "Number of store queue entries")
     LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
@@ -118,8 +103,6 @@ class DerivO3CPU(BaseCPU):
     numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
     numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
 
-    instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by")
-
     smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
     smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy")
     smtLSQPolicy    = Param.String('Partitioned', "SMT LSQ Sharing Policy")
@@ -130,6 +113,7 @@ class DerivO3CPU(BaseCPU):
     smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
     smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
 
+    branchPred = BranchPredictor(numThreads = Parent.numThreads)
     needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
                           "Enable TSO Memory model")
 
diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
index e97f4527b..50b5a8ea4 100755
--- a/src/cpu/o3/SConscript
+++ b/src/cpu/o3/SConscript
@@ -43,7 +43,6 @@ if 'O3CPU' in env['CPU_MODELS']:
     SimObject('O3CPU.py')
 
     Source('base_dyn_inst.cc')
-    Source('bpred_unit.cc')
     Source('commit.cc')
     Source('cpu.cc')
     Source('deriv.cc')
diff --git a/src/cpu/o3/bpred_unit.cc b/src/cpu/o3/bpred_unit.cc
deleted file mode 100644
index 08fd4e8ea..000000000
--- a/src/cpu/o3/bpred_unit.cc
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2004-2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#include "cpu/o3/bpred_unit_impl.hh"
-#include "cpu/o3/isa_specific.hh"
-
-template class BPredUnit<O3CPUImpl>;
diff --git a/src/cpu/o3/bpred_unit.hh b/src/cpu/o3/bpred_unit.hh
deleted file mode 100644
index 3f83f9bef..000000000
--- a/src/cpu/o3/bpred_unit.hh
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * Copyright (c) 2011-2012 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder.  You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#ifndef __CPU_O3_BPRED_UNIT_HH__
-#define __CPU_O3_BPRED_UNIT_HH__
-
-#include <list>
-
-#include "base/statistics.hh"
-#include "base/types.hh"
-#include "cpu/pred/2bit_local.hh"
-#include "cpu/pred/btb.hh"
-#include "cpu/pred/ras.hh"
-#include "cpu/pred/tournament.hh"
-#include "cpu/inst_seq.hh"
-
-struct DerivO3CPUParams;
-
-/**
- * Basically a wrapper class to hold both the branch predictor
- * and the BTB.
- */
-template<class Impl>
-class BPredUnit
-{
-  private:
-    typedef typename Impl::DynInstPtr DynInstPtr;
-
-    enum PredType {
-        Local,
-        Tournament
-    };
-
-    PredType predictor;
-
-    const std::string _name;
-
-  public:
-
-    /**
-     * @param params The params object, that has the size of the BP and BTB.
-     */
-    BPredUnit(DerivO3CPUParams *params);
-
-    const std::string &name() const { return _name; }
-
-    /**
-     * Registers statistics.
-     */
-    void regStats();
-
-    /** Perform sanity checks after a drain. */
-    void drainSanityCheck() const;
-
-    /** Take over execution from another CPU's thread. */
-    void takeOverFrom();
-
-    /**
-     * Predicts whether or not the instruction is a taken branch, and the
-     * target of the branch if it is taken.
-     * @param inst The branch instruction.
-     * @param PC The predicted PC is passed back through this parameter.
-     * @param tid The thread id.
-     * @return Returns if the branch is taken or not.
-     */
-    bool predict(DynInstPtr &inst, TheISA::PCState &pc, ThreadID tid);
-
-    // @todo: Rename this function.
-    void BPUncond(void * &bp_history);
-
-    /**
-     * Tells the branch predictor to commit any updates until the given
-     * sequence number.
-     * @param done_sn The sequence number to commit any older updates up until.
-     * @param tid The thread id.
-     */
-    void update(const InstSeqNum &done_sn, ThreadID tid);
-
-    /**
-     * Squashes all outstanding updates until a given sequence number.
-     * @param squashed_sn The sequence number to squash any younger updates up
-     * until.
-     * @param tid The thread id.
-     */
-    void squash(const InstSeqNum &squashed_sn, ThreadID tid);
-
-    /**
-     * Squashes all outstanding updates until a given sequence number, and
-     * corrects that sn's update with the proper address and taken/not taken.
-     * @param squashed_sn The sequence number to squash any younger updates up
-     * until.
-     * @param corr_target The correct branch target.
-     * @param actually_taken The correct branch direction.
-     * @param tid The thread id.
-     */
-    void squash(const InstSeqNum &squashed_sn,
-                const TheISA::PCState &corr_target,
-                bool actually_taken, ThreadID tid);
-
-    /**
-     * @param bp_history Pointer to the history object.  The predictor
-     * will need to update any state and delete the object.
-     */
-    void BPSquash(void *bp_history);
-
-    /**
-     * Looks up a given PC in the BP to see if it is taken or not taken.
-     * @param inst_PC The PC to look up.
-     * @param bp_history Pointer that will be set to an object that
-     * has the branch predictor state associated with the lookup.
-     * @return Whether the branch is taken or not taken.
-     */
-    bool BPLookup(Addr instPC, void * &bp_history);
-
-     /**
-     * If a branch is not taken, because the BTB address is invalid or missing,
-     * this function sets the appropriate counter in the global and local
-     * predictors to not taken.
-     * @param inst_PC The PC to look up the local predictor.
-     * @param bp_history Pointer that will be set to an object that
-     * has the branch predictor state associated with the lookup.
-     */
-    void BPBTBUpdate(Addr instPC, void * &bp_history);
-
-    /**
-     * Looks up a given PC in the BTB to see if a matching entry exists.
-     * @param inst_PC The PC to look up.
-     * @return Whether the BTB contains the given PC.
-     */
-    bool BTBValid(Addr instPC)
-    { return BTB.valid(instPC, 0); }
-
-    /**
-     * Looks up a given PC in the BTB to get the predicted target.
-     * @param inst_PC The PC to look up.
-     * @return The address of the target of the branch.
-     */
-    TheISA::PCState BTBLookup(Addr instPC)
-    { return BTB.lookup(instPC, 0); }
-
-    /**
-     * Updates the BP with taken/not taken information.
-     * @param inst_PC The branch's PC that will be updated.
-     * @param taken Whether the branch was taken or not taken.
-     * @param bp_history Pointer to the branch predictor state that is
-     * associated with the branch lookup that is being updated.
-     * @param squashed Set to true when this function is called during a
-     * squash operation.
-     * @todo Make this update flexible enough to handle a global predictor.
-     */
-    void BPUpdate(Addr instPC, bool taken, void *bp_history, bool squashed);
-
-    /**
-     * Updates the BTB with the target of a branch.
-     * @param inst_PC The branch's PC that will be updated.
-     * @param target_PC The branch's target that will be added to the BTB.
-     */
-    void BTBUpdate(Addr instPC, const TheISA::PCState &target)
-    { BTB.update(instPC, target, 0); }
-
-    void dump();
-
-  private:
-    struct PredictorHistory {
-        /**
-         * Makes a predictor history struct that contains any
-         * information needed to update the predictor, BTB, and RAS.
-         */
-        PredictorHistory(const InstSeqNum &seq_num, Addr instPC,
-                         bool pred_taken, void *bp_history,
-                         ThreadID _tid)
-            : seqNum(seq_num), pc(instPC), bpHistory(bp_history), RASTarget(0),
-              RASIndex(0), tid(_tid), predTaken(pred_taken), usedRAS(0), pushedRAS(0),
-              wasCall(0), wasReturn(0), validBTB(0)
-        {}
-
-        bool operator==(const PredictorHistory &entry) const {
-            return this->seqNum == entry.seqNum;
-        }
-
-        /** The sequence number for the predictor history entry. */
-        InstSeqNum seqNum;
-
-        /** The PC associated with the sequence number. */
-        Addr pc;
-
-        /** Pointer to the history object passed back from the branch
-         * predictor.  It is used to update or restore state of the
-         * branch predictor.
-         */
-        void *bpHistory;
-
-        /** The RAS target (only valid if a return). */
-        TheISA::PCState RASTarget;
-
-        /** The RAS index of the instruction (only valid if a call). */
-        unsigned RASIndex;
-
-        /** The thread id. */
-        ThreadID tid;
-
-        /** Whether or not it was predicted taken. */
-        bool predTaken;
-
-        /** Whether or not the RAS was used. */
-        bool usedRAS;
-
-        /* Wether or not the RAS was pushed */
-        bool pushedRAS;
-
-        /** Whether or not the instruction was a call. */
-        bool wasCall;
-
-        /** Whether or not the instruction was a return. */
-        bool wasReturn;
-        /** Whether or not the instruction had a valid BTB entry. */
-        bool validBTB;
-    };
-
-    typedef std::list<PredictorHistory> History;
-    typedef typename History::iterator HistoryIt;
-
-    /**
-     * The per-thread predictor history. This is used to update the predictor
-     * as instructions are committed, or restore it to the proper state after
-     * a squash.
-     */
-    History predHist[Impl::MaxThreads];
-
-    /** The local branch predictor. */
-    LocalBP *localBP;
-
-    /** The tournament branch predictor. */
-    TournamentBP *tournamentBP;
-
-    /** The BTB. */
-    DefaultBTB BTB;
-
-    /** The per-thread return address stack. */
-    ReturnAddrStack RAS[Impl::MaxThreads];
-
-    /** Stat for number of BP lookups. */
-    Stats::Scalar lookups;
-    /** Stat for number of conditional branches predicted. */
-    Stats::Scalar condPredicted;
-    /** Stat for number of conditional branches predicted incorrectly. */
-    Stats::Scalar condIncorrect;
-    /** Stat for number of BTB lookups. */
-    Stats::Scalar BTBLookups;
-    /** Stat for number of BTB hits. */
-    Stats::Scalar BTBHits;
-    /** Stat for number of times the BTB is correct. */
-    Stats::Scalar BTBCorrect;
-    /** Stat for number of times the RAS is used to get a target. */
-    Stats::Scalar usedRAS;
-    /** Stat for number of times the RAS is incorrect. */
-    Stats::Scalar RASIncorrect;
-};
-
-#endif // __CPU_O3_BPRED_UNIT_HH__
diff --git a/src/cpu/o3/bpred_unit_impl.hh b/src/cpu/o3/bpred_unit_impl.hh
deleted file mode 100644
index 43e801710..000000000
--- a/src/cpu/o3/bpred_unit_impl.hh
+++ /dev/null
@@ -1,515 +0,0 @@
-/*
- * Copyright (c) 2011-2012 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder.  You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#include <algorithm>
-
-#include "arch/isa_traits.hh"
-#include "arch/types.hh"
-#include "arch/utility.hh"
-#include "base/trace.hh"
-#include "config/the_isa.hh"
-#include "cpu/o3/bpred_unit.hh"
-#include "debug/Fetch.hh"
-#include "params/DerivO3CPU.hh"
-
-template<class Impl>
-BPredUnit<Impl>::BPredUnit(DerivO3CPUParams *params)
-    : _name(params->name + ".BPredUnit"),
-      BTB(params->BTBEntries,
-          params->BTBTagSize,
-          params->instShiftAmt)
-{
-    // Setup the selected predictor.
-    if (params->predType == "local") {
-        localBP = new LocalBP(params->localPredictorSize,
-                              params->localCtrBits,
-                              params->instShiftAmt);
-        predictor = Local;
-    } else if (params->predType == "tournament") {
-        tournamentBP = new TournamentBP(params->localCtrBits,
-                                        params->localHistoryTableSize,
-                                        params->localHistoryBits,
-                                        params->globalPredictorSize,
-                                        params->globalHistoryBits,
-                                        params->globalCtrBits,
-                                        params->choicePredictorSize,
-                                        params->choiceCtrBits,
-                                        params->instShiftAmt);
-        predictor = Tournament;
-    } else {
-        fatal("Invalid BP selected!");
-    }
-
-    for (int i=0; i < Impl::MaxThreads; i++)
-        RAS[i].init(params->RASSize);
-}
-
-template <class Impl>
-void
-BPredUnit<Impl>::regStats()
-{
-    lookups
-        .name(name() + ".lookups")
-        .desc("Number of BP lookups")
-        ;
-
-    condPredicted
-        .name(name() + ".condPredicted")
-        .desc("Number of conditional branches predicted")
-        ;
-
-    condIncorrect
-        .name(name() + ".condIncorrect")
-        .desc("Number of conditional branches incorrect")
-        ;
-
-    BTBLookups
-        .name(name() + ".BTBLookups")
-        .desc("Number of BTB lookups")
-        ;
-
-    BTBHits
-        .name(name() + ".BTBHits")
-        .desc("Number of BTB hits")
-        ;
-
-    BTBCorrect
-        .name(name() + ".BTBCorrect")
-        .desc("Number of correct BTB predictions (this stat may not "
-              "work properly.")
-        ;
-
-    usedRAS
-        .name(name() + ".usedRAS")
-        .desc("Number of times the RAS was used to get a target.")
-        ;
-
-    RASIncorrect
-        .name(name() + ".RASInCorrect")
-        .desc("Number of incorrect RAS predictions.")
-        ;
-}
-
-template <class Impl>
-void
-BPredUnit<Impl>::drainSanityCheck() const
-{
-    // We shouldn't have any outstanding requests when we resume from
-    // a drained system.
-    for (int i = 0; i < Impl::MaxThreads; ++i)
-        assert(predHist[i].empty());
-}
-
-template <class Impl>
-void
-BPredUnit<Impl>::takeOverFrom()
-{
-    // Can reset all predictor state, but it's not necessarily better
-    // than leaving it be.
-/*
-    for (int i = 0; i < Impl::MaxThreads; ++i)
-        RAS[i].reset();
-
-    BP.reset();
-    BTB.reset();
-*/
-}
-
-template <class Impl>
-bool
-BPredUnit<Impl>::predict(DynInstPtr &inst, TheISA::PCState &pc, ThreadID tid)
-{
-    // See if branch predictor predicts taken.
-    // If so, get its target addr either from the BTB or the RAS.
-    // Save off record of branch stuff so the RAS can be fixed
-    // up once it's done.
-
-    bool pred_taken = false;
-    TheISA::PCState target = pc;
-
-    ++lookups;
-
-    void *bp_history = NULL;
-
-    if (inst->isUncondCtrl()) {
-        DPRINTF(Fetch, "BranchPred: [tid:%i]: Unconditional control.\n", tid);
-        pred_taken = true;
-        // Tell the BP there was an unconditional branch.
-        BPUncond(bp_history);
-    } else {
-        ++condPredicted;
-        pred_taken = BPLookup(pc.instAddr(), bp_history);
-
-        DPRINTF(Fetch, "BranchPred:[tid:%i]: [sn:%i] Branch predictor"
-                " predicted %i for PC %s\n",
-                tid, inst->seqNum,  pred_taken, inst->pcState());
-    }
-
-    DPRINTF(Fetch, "BranchPred: [tid:%i]: [sn:%i] Creating prediction history "
-                "for PC %s\n",
-            tid, inst->seqNum, inst->pcState());
-
-    PredictorHistory predict_record(inst->seqNum, pc.instAddr(),
-                                    pred_taken, bp_history, tid);
-
-    // Now lookup in the BTB or RAS.
-    if (pred_taken) {
-        if (inst->isReturn()) {
-            ++usedRAS;
-            predict_record.wasReturn = true;
-            // If it's a function return call, then look up the address
-            // in the RAS.
-            TheISA::PCState rasTop = RAS[tid].top();
-            target = TheISA::buildRetPC(pc, rasTop);
-
-            // Record the top entry of the RAS, and its index.
-            predict_record.usedRAS = true;
-            predict_record.RASIndex = RAS[tid].topIdx();
-            predict_record.RASTarget = rasTop;
-
-            RAS[tid].pop();
-
-            DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %s is a return, "
-                    "RAS predicted target: %s, RAS index: %i.\n",
-                    tid, inst->pcState(), target, predict_record.RASIndex);
-        } else {
-            ++BTBLookups;
-
-            if (inst->isCall()) {
-                RAS[tid].push(pc);
-                predict_record.pushedRAS = true;
-                // Record that it was a call so that the top RAS entry can
-                // be popped off if the speculation is incorrect.
-                predict_record.wasCall = true;
-
-                DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %s was a "
-                        "call, adding %s to the RAS index: %i.\n",
-                        tid, inst->pcState(), pc, RAS[tid].topIdx());
-            }
-
-            if (BTB.valid(pc.instAddr(), tid)) {
-                ++BTBHits;
-                predict_record.validBTB = true;
-
-                // If it's not a return, use the BTB to get the target addr.
-                target = BTB.lookup(pc.instAddr(), tid);
-
-                DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %s predicted"
-                        " target is %s.\n", tid, inst->pcState(), target);
-
-            } else {
-                DPRINTF(Fetch, "BranchPred: [tid:%i]: BTB doesn't have a "
-                        "valid entry.\n",tid);
-                pred_taken = false;
-                // The Direction of the branch predictor is altered because the
-                // BTB did not have an entry
-                // The predictor needs to be updated accordingly
-                if (!inst->isCall() && !inst->isReturn()) {
-                      BPBTBUpdate(pc.instAddr(), bp_history);
-                      DPRINTF(Fetch, "BranchPred: [tid:%i]:[sn:%i] BPBTBUpdate"
-                              " called for %s\n",
-                              tid, inst->seqNum, inst->pcState());
-                } else if (inst->isCall() && !inst->isUncondCtrl()) {
-                      RAS[tid].pop();
-                      predict_record.pushedRAS = false;
-                }
-                TheISA::advancePC(target, inst->staticInst);
-            }
-
-        }
-    } else {
-        if (inst->isReturn()) {
-           predict_record.wasReturn = true;
-        }
-        TheISA::advancePC(target, inst->staticInst);
-    }
-
-    pc = target;
-
-    predHist[tid].push_front(predict_record);
-
-    DPRINTF(Fetch, "BranchPred: [tid:%i]: [sn:%i]: History entry added."
-            "predHist.size(): %i\n", tid, inst->seqNum, predHist[tid].size());
-
-    return pred_taken;
-}
-
-template <class Impl>
-void
-BPredUnit<Impl>::update(const InstSeqNum &done_sn, ThreadID tid)
-{
-    DPRINTF(Fetch, "BranchPred: [tid:%i]: Committing branches until "
-            "[sn:%lli].\n", tid, done_sn);
-
-    while (!predHist[tid].empty() &&
-           predHist[tid].back().seqNum <= done_sn) {
-        // Update the branch predictor with the correct results.
-        BPUpdate(predHist[tid].back().pc,
-                 predHist[tid].back().predTaken,
-                 predHist[tid].back().bpHistory, false);
-
-        predHist[tid].pop_back();
-    }
-}
-
-template <class Impl>
-void
-BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn, ThreadID tid)
-{
-    History &pred_hist = predHist[tid];
-
-    while (!pred_hist.empty() &&
-           pred_hist.front().seqNum > squashed_sn) {
-        if (pred_hist.front().usedRAS) {
-            DPRINTF(Fetch, "BranchPred: [tid:%i]: Restoring top of RAS to: %i,"
-                    " target: %s.\n", tid,
-                    pred_hist.front().RASIndex, pred_hist.front().RASTarget);
-
-            RAS[tid].restore(pred_hist.front().RASIndex,
-                             pred_hist.front().RASTarget);
-        } else if(pred_hist.front().wasCall && pred_hist.front().pushedRAS) {
-                 // Was a call but predicated false. Pop RAS here
-                 DPRINTF(Fetch, "BranchPred: [tid: %i] Squashing"
-                         "  Call [sn:%i] PC: %s Popping RAS\n", tid,
-                         pred_hist.front().seqNum, pred_hist.front().pc);
-                 RAS[tid].pop();
-           }
-
-        // This call should delete the bpHistory.
-        BPSquash(pred_hist.front().bpHistory);
-
-        DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing history for [sn:%i] "
-                "PC %s.\n", tid, pred_hist.front().seqNum,
-                pred_hist.front().pc);
-
-        pred_hist.pop_front();
-
-        DPRINTF(Fetch, "[tid:%i]: predHist.size(): %i\n",
-                tid, predHist[tid].size());
-    }
-
-}
-
-template <class Impl>
-void
-BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn,
-                        const TheISA::PCState &corrTarget,
-                        bool actually_taken,
-                        ThreadID tid)
-{
-    // Now that we know that a branch was mispredicted, we need to undo
-    // all the branches that have been seen up until this branch and
-    // fix up everything.
-    // NOTE: This should be call conceivably in 2 scenarios:
-    // (1) After an branch is executed, it updates its status in the ROB
-    //     The commit stage then checks the ROB update and sends a signal to
-    //     the fetch stage to squash history after the mispredict
-    // (2) In the decode stage, you can find out early if a unconditional
-    //     PC-relative, branch was predicted incorrectly. If so, a signal
-    //     to the fetch stage is sent to squash history after the mispredict
-
-    History &pred_hist = predHist[tid];
-
-    ++condIncorrect;
-
-    DPRINTF(Fetch, "BranchPred: [tid:%i]: Squashing from sequence number %i, "
-            "setting target to %s.\n",
-            tid, squashed_sn, corrTarget);
-
-    // Squash All Branches AFTER this mispredicted branch
-    squash(squashed_sn, tid);
-
-    // If there's a squash due to a syscall, there may not be an entry
-    // corresponding to the squash.  In that case, don't bother trying to
-    // fix up the entry.
-    if (!pred_hist.empty()) {
-
-        HistoryIt hist_it = pred_hist.begin();
-        //HistoryIt hist_it = find(pred_hist.begin(), pred_hist.end(),
-        //                       squashed_sn);
-
-        //assert(hist_it != pred_hist.end());
-        if (pred_hist.front().seqNum != squashed_sn) {
-            DPRINTF(Fetch, "Front sn %i != Squash sn %i\n",
-                    pred_hist.front().seqNum, squashed_sn);
-
-            assert(pred_hist.front().seqNum == squashed_sn);
-        }
-
-
-        if ((*hist_it).usedRAS) {
-            ++RASIncorrect;
-        }
-
-        BPUpdate((*hist_it).pc, actually_taken,
-                 pred_hist.front().bpHistory, true);
-        if (actually_taken) {
-            if (hist_it->wasReturn && !hist_it->usedRAS) {
-                 DPRINTF(Fetch, "BranchPred: [tid: %i] Incorrectly predicted"
-                           "  return [sn:%i] PC: %s\n", tid, hist_it->seqNum,
-                            hist_it->pc);
-                 RAS[tid].pop();
-            }
-           DPRINTF(Fetch,"BranchPred: [tid: %i] BTB Update called for [sn:%i]"
-                            " PC: %s\n", tid,hist_it->seqNum, hist_it->pc);
-
-
-            BTB.update((*hist_it).pc, corrTarget, tid);
-
-        } else {
-           //Actually not Taken
-           if (hist_it->usedRAS) {
-                DPRINTF(Fetch,"BranchPred: [tid: %i] Incorrectly predicted"
-                           "  return [sn:%i] PC: %s Restoring RAS\n", tid,
-                           hist_it->seqNum, hist_it->pc);
-                DPRINTF(Fetch, "BranchPred: [tid:%i]: Restoring top of RAS"
-                               " to: %i, target: %s.\n", tid,
-                              hist_it->RASIndex, hist_it->RASTarget);
-                RAS[tid].restore(hist_it->RASIndex, hist_it->RASTarget);
-
-           } else if (hist_it->wasCall && hist_it->pushedRAS) {
-                 //Was a Call but predicated false. Pop RAS here
-                 DPRINTF(Fetch, "BranchPred: [tid: %i] Incorrectly predicted"
-                           "  Call [sn:%i] PC: %s Popping RAS\n", tid,
-                           hist_it->seqNum, hist_it->pc);
-                 RAS[tid].pop();
-           }
-        }
-        DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing history for [sn:%i]"
-                       " PC %s  Actually Taken: %i\n", tid, hist_it->seqNum,
-                       hist_it->pc, actually_taken);
-
-        pred_hist.erase(hist_it);
-
-        DPRINTF(Fetch, "[tid:%i]: predHist.size(): %i\n", tid,
-                                         predHist[tid].size());
-    }
-}
-
-template <class Impl>
-void
-BPredUnit<Impl>::BPUncond(void * &bp_history)
-{
-    // Only the tournament predictor cares about unconditional branches.
-    if (predictor == Tournament) {
-        tournamentBP->uncondBr(bp_history);
-    }
-}
-
-template <class Impl>
-void
-BPredUnit<Impl>::BPSquash(void *bp_history)
-{
-    if (predictor == Local) {
-        localBP->squash(bp_history);
-    } else if (predictor == Tournament) {
-        tournamentBP->squash(bp_history);
-    } else {
-        panic("Predictor type is unexpected value!");
-    }
-}
-
-template <class Impl>
-bool
-BPredUnit<Impl>::BPLookup(Addr instPC, void * &bp_history)
-{
-    if (predictor == Local) {
-        return localBP->lookup(instPC, bp_history);
-    } else if (predictor == Tournament) {
-        return tournamentBP->lookup(instPC, bp_history);
-    } else {
-        panic("Predictor type is unexpected value!");
-    }
-}
-
-template <class Impl>
-void
-BPredUnit<Impl>::BPBTBUpdate(Addr instPC, void * &bp_history)
-{
-    if (predictor == Local) {
-        return localBP->BTBUpdate(instPC, bp_history);
-    } else if (predictor == Tournament) {
-        return tournamentBP->BTBUpdate(instPC, bp_history);
-    } else {
-        panic("Predictor type is unexpected value!");
-    }
-}
-
-template <class Impl>
-void
-BPredUnit<Impl>::BPUpdate(Addr instPC, bool taken, void *bp_history,
-                 bool squashed)
-{
-    if (predictor == Local) {
-        localBP->update(instPC, taken, bp_history);
-    } else if (predictor == Tournament) {
-        tournamentBP->update(instPC, taken, bp_history, squashed);
-    } else {
-        panic("Predictor type is unexpected value!");
-    }
-}
-
-template <class Impl>
-void
-BPredUnit<Impl>::dump()
-{
-    HistoryIt pred_hist_it;
-
-    for (int i = 0; i < Impl::MaxThreads; ++i) {
-        if (!predHist[i].empty()) {
-            pred_hist_it = predHist[i].begin();
-
-            cprintf("predHist[%i].size(): %i\n", i, predHist[i].size());
-
-            while (pred_hist_it != predHist[i].end()) {
-                cprintf("[sn:%lli], PC:%#x, tid:%i, predTaken:%i, "
-                        "bpHistory:%#x\n",
-                        pred_hist_it->seqNum, pred_hist_it->pc,
-                        pred_hist_it->tid, pred_hist_it->predTaken,
-                        pred_hist_it->bpHistory);
-                pred_hist_it++;
-            }
-
-            cprintf("\n");
-        }
-    }
-}
diff --git a/src/cpu/o3/cpu_policy.hh b/src/cpu/o3/cpu_policy.hh
index ed0c31133..eea49ad52 100644
--- a/src/cpu/o3/cpu_policy.hh
+++ b/src/cpu/o3/cpu_policy.hh
@@ -31,7 +31,6 @@
 #ifndef __CPU_O3_CPU_POLICY_HH__
 #define __CPU_O3_CPU_POLICY_HH__
 
-#include "cpu/o3/bpred_unit.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/commit.hh"
 #include "cpu/o3/decode.hh"
@@ -60,10 +59,6 @@
 template<class Impl>
 struct SimpleCPUPolicy
 {
-    /** Typedef for the branch prediction unit (which includes the BP,
-     * RAS, and BTB).
-     */
-    typedef ::BPredUnit<Impl> BPredUnit;
     /** Typedef for the register file.  Most classes assume a unified
      * physical register file.
      */
diff --git a/src/cpu/o3/deriv.cc b/src/cpu/o3/deriv.cc
index fb10934d5..9f41b989f 100644
--- a/src/cpu/o3/deriv.cc
+++ b/src/cpu/o3/deriv.cc
@@ -65,7 +65,5 @@ DerivO3CPUParams::create()
     else
         smtFetchPolicy = smtFetchPolicy;
 
-    instShiftAmt = 2;
-
     return new DerivO3CPU(this);
 }
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index fb17a9247..23245d496 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -49,6 +49,7 @@
 #include "base/statistics.hh"
 #include "config/the_isa.hh"
 #include "cpu/pc_event.hh"
+#include "cpu/pred/bpred_unit.hh"
 #include "cpu/timebuf.hh"
 #include "cpu/translation.hh"
 #include "mem/packet.hh"
@@ -76,7 +77,6 @@ class DefaultFetch
     typedef typename Impl::O3CPU O3CPU;
 
     /** Typedefs from the CPU policy. */
-    typedef typename CPUPol::BPredUnit BPredUnit;
     typedef typename CPUPol::FetchStruct FetchStruct;
     typedef typename CPUPol::TimeStruct TimeStruct;
 
@@ -405,7 +405,7 @@ class DefaultFetch
     typename TimeBuffer<FetchStruct>::wire toDecode;
 
     /** BPredUnit. */
-    BPredUnit branchPred;
+    BPredUnit *branchPred;
 
     TheISA::PCState pc[Impl::MaxThreads];
 
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index f531203d9..07033fc8a 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -73,7 +73,6 @@ using namespace std;
 template<class Impl>
 DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
     : cpu(_cpu),
-      branchPred(params),
       decodeToFetchDelay(params->decodeToFetchDelay),
       renameToFetchDelay(params->renameToFetchDelay),
       iewToFetchDelay(params->iewToFetchDelay),
@@ -129,6 +128,8 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
         cacheData[i] = NULL;
         decoder[i] = new TheISA::Decoder;
     }
+
+    branchPred = params->branchPred;
 }
 
 template <class Impl>
@@ -259,8 +260,6 @@ DefaultFetch<Impl>::regStats()
         .desc("Number of inst fetches per cycle")
         .flags(Stats::total);
     fetchRate = fetchedInsts / cpu->numCycles;
-
-    branchPred.regStats();
 }
 
 template<class Impl>
@@ -437,7 +436,7 @@ DefaultFetch<Impl>::drainSanityCheck() const
         assert(fetchStatus[i] == Idle || stalls[i].drain);
     }
 
-    branchPred.drainSanityCheck();
+    branchPred->drainSanityCheck();
 }
 
 template <class Impl>
@@ -470,7 +469,6 @@ DefaultFetch<Impl>::takeOverFrom()
     assert(cpu->getInstPort().isConnected());
     resetStage();
 
-    branchPred.takeOverFrom();
 }
 
 template <class Impl>
@@ -537,7 +535,8 @@ DefaultFetch<Impl>::lookupAndUpdateNextPC(
     }
 
     ThreadID tid = inst->threadNumber;
-    predict_taken = branchPred.predict(inst, nextPC, tid);
+    predict_taken = branchPred->predict(inst->staticInst, inst->seqNum,
+                                        nextPC, tid);
 
     if (predict_taken) {
         DPRINTF(Fetch, "[tid:%i]: [sn:%i]:  Branch predicted to be taken to %s.\n",
@@ -990,12 +989,12 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
         // invalid state we generated in after sequence number
         if (fromCommit->commitInfo[tid].mispredictInst &&
             fromCommit->commitInfo[tid].mispredictInst->isControl()) {
-            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
+            branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum,
                               fromCommit->commitInfo[tid].pc,
                               fromCommit->commitInfo[tid].branchTaken,
                               tid);
         } else {
-            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
+            branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum,
                               tid);
         }
 
@@ -1003,7 +1002,7 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
     } else if (fromCommit->commitInfo[tid].doneSeqNum) {
         // Update the branch predictor if it wasn't a squashed instruction
         // that was broadcasted.
-        branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
+        branchPred->update(fromCommit->commitInfo[tid].doneSeqNum, tid);
     }
 
     // Check ROB squash signals from commit.
@@ -1023,12 +1022,12 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
 
         // Update the branch predictor.
         if (fromDecode->decodeInfo[tid].branchMispredict) {
-            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
+            branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum,
                               fromDecode->decodeInfo[tid].nextPC,
                               fromDecode->decodeInfo[tid].branchTaken,
                               tid);
         } else {
-            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
+            branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum,
                               tid);
         }
 
diff --git a/src/cpu/o3/sat_counter.cc b/src/cpu/o3/sat_counter.cc
deleted file mode 100644
index 68d3ef627..000000000
--- a/src/cpu/o3/sat_counter.cc
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#include "base/misc.hh"
-#include "cpu/o3/sat_counter.hh"
-
-SatCounter::SatCounter()
-    : initialVal(0), counter(0)
-{
-}
-
-SatCounter::SatCounter(unsigned bits)
-    : initialVal(0), maxVal((1 << bits) - 1), counter(0)
-{
-}
-
-SatCounter::SatCounter(unsigned bits, uint8_t initial_val)
-    : initialVal(initialVal), maxVal((1 << bits) - 1), counter(initial_val)
-{
-    // Check to make sure initial value doesn't exceed the max counter value.
-    if (initial_val > maxVal) {
-        fatal("BP: Initial counter value exceeds max size.");
-    }
-}
-
-void
-SatCounter::setBits(unsigned bits)
-{
-    maxVal = (1 << bits) - 1;
-}
diff --git a/src/cpu/o3/sat_counter.hh b/src/cpu/o3/sat_counter.hh
deleted file mode 100644
index 17ff8546b..000000000
--- a/src/cpu/o3/sat_counter.hh
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright (c) 2005-2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#ifndef __CPU_O3_SAT_COUNTER_HH__
-#define __CPU_O3_SAT_COUNTER_HH__
-
-#include "base/misc.hh"
-#include "base/types.hh"
-
-/**
- * Private counter class for the internal saturating counters.
- * Implements an n bit saturating counter and provides methods to
- * increment, decrement, and read it.
- * @todo Consider making this something that more closely mimics a
- * built in class so you can use ++ or --.
- */
-class SatCounter
-{
-  public:
-    /**
-     * Constructor for the counter.
-     */
-    SatCounter()
-        : initialVal(0), counter(0)
-    { }
-
-    /**
-     * Constructor for the counter.
-     * @param bits How many bits the counter will have.
-     */
-    SatCounter(unsigned bits)
-        : initialVal(0), maxVal((1 << bits) - 1), counter(0)
-    { }
-
-    /**
-     * Constructor for the counter.
-     * @param bits How many bits the counter will have.
-     * @param initial_val Starting value for each counter.
-     */
-    SatCounter(unsigned bits, uint8_t initial_val)
-        : initialVal(initial_val), maxVal((1 << bits) - 1),
-          counter(initial_val)
-    {
-        // Check to make sure initial value doesn't exceed the max
-        // counter value.
-        if (initial_val > maxVal) {
-            fatal("BP: Initial counter value exceeds max size.");
-        }
-    }
-
-    /**
-     * Sets the number of bits.
-     */
-    void setBits(unsigned bits) { maxVal = (1 << bits) - 1; }
-
-    void reset() { counter = initialVal; }
-
-    /**
-     * Increments the counter's current value.
-     */
-    void increment()
-    {
-        if (counter < maxVal) {
-            ++counter;
-        }
-    }
-
-    /**
-     * Decrements the counter's current value.
-     */
-    void decrement()
-    {
-        if (counter > 0) {
-            --counter;
-        }
-    }
-
-    /**
-     * Read the counter's value.
-     */
-    const uint8_t read() const
-    { return counter; }
-
-  private:
-    uint8_t initialVal;
-    uint8_t maxVal;
-    uint8_t counter;
-};
-
-#endif // __CPU_O3_SAT_COUNTER_HH__