diff options
| author | Gabor Dozsa <gabor.dozsa@arm.com> | 2018-02-08 15:07:46 +0000 |
|---|---|---|
| committer | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2019-05-31 08:39:05 +0000 |
| commit | 019e3204ba54e23daf597becf36bb92f7272b0d3 (patch) | |
| tree | 600935f2ef5d04737bf7413120bfe533109b11f6 /src/cpu/o3 | |
| parent | 3b04ba58b81f5bee45c7c5111c93605eac850f9c (diff) | |
| download | gem5-019e3204ba54e23daf597becf36bb92f7272b0d3.tar.xz | |
cpu-o3: Increase LSQ buffer sizes to match max vector length
Change-Id: I5890c7cfa147125ce3389001f85d56d4b5a9911d
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13525
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/lsq_unit.hh | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 5c64971c1..d3f1d0712 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -51,6 +51,7 @@ #include <queue> #include "arch/generic/debugfaults.hh" +#include "arch/generic/vec_reg.hh" #include "arch/isa_traits.hh" #include "arch/locked_mem.hh" #include "arch/mmapped_ipr.hh" @@ -80,6 +81,8 @@ template <class Impl> class LSQUnit { public: + static constexpr auto MaxDataBytes = MaxVecRegLenInBytes; + typedef typename Impl::O3CPU O3CPU; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::CPUPol::IEW IEW; @@ -97,7 +100,7 @@ class LSQUnit /** The request. */ LSQRequest* req; /** The size of the operation. */ - uint8_t _size; + uint32_t _size; /** Valid entry. */ bool _valid; public: @@ -142,8 +145,8 @@ class LSQUnit /** Member accessors. */ /** @{ */ bool valid() const { return _valid; } - uint8_t& size() { return _size; } - const uint8_t& size() const { return _size; } + uint32_t& size() { return _size; } + const uint32_t& size() const { return _size; } const DynInstPtr& instruction() const { return inst; } /** @} */ }; @@ -152,7 +155,7 @@ class LSQUnit { private: /** The store data. */ - char _data[64]; // TODO: 64 should become a parameter + char _data[MaxDataBytes]; /** Whether or not the store can writeback. */ bool _canWB; /** Whether or not the store is committed. */ @@ -659,7 +662,7 @@ LSQUnit<Impl>::read(LSQRequest *req, int load_idx) if (req->mainRequest()->isMmappedIpr()) { assert(!load_inst->memData); - load_inst->memData = new uint8_t[64]; + load_inst->memData = new uint8_t[MaxDataBytes]; ThreadContext *thread = cpu->tcBase(lsqID); PacketPtr main_pkt = new Packet(req->mainRequest(), MemCmd::ReadReq); |