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| author | Andrea Mondelli <Andrea.Mondelli@ucf.edu> | 2019-03-25 12:41:54 -0400 |
|---|---|---|
| committer | Andrea Mondelli <Andrea.Mondelli@ucf.edu> | 2019-04-03 16:48:55 +0000 |
| commit | 5084b90e2af6e5bfad3119b4431a3b063ef3b799 (patch) | |
| tree | fa013c4f0e55cc67ed8746d72173619230fb1b99 /src/cpu/o3 | |
| parent | 5caa4517345d4833af44e510f78717ee7e0ad8d4 (diff) | |
| download | gem5-5084b90e2af6e5bfad3119b4431a3b063ef3b799.tar.xz | |
arch-mips: added missing override specifier (o3)
Change-Id: Ic538825a2964fd62def672b933a83067a15bd12a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17648
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/dyn_inst.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 640ebf850..24c59a25d 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -432,14 +432,14 @@ class BaseO3DynInst : public BaseDynInst<Impl> #if THE_ISA == MIPS_ISA RegVal - readRegOtherThread(const RegId& misc_reg, ThreadID tid) + readRegOtherThread(const RegId& misc_reg, ThreadID tid) override { panic("MIPS MT not defined for O3 CPU.\n"); return 0; } void - setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) + setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) override { panic("MIPS MT not defined for O3 CPU.\n"); } |