cpu, arch: Replace the CCReg type with RegVal.

Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.

Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Reviewed-on: https://gem5-review.googlesource.com/c/14515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 files changed, 22 insertions, 21 deletions

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 0cea74861..f5aa9f712 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1379,7 +1379,7 @@ FullO3CPU<Impl>::getWritableVecPredReg(PhysRegIdPtr phys_reg)
 }
 
 template <class Impl>
-CCReg
+RegVal
 FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
 {
     ccRegfileReads++;
@@ -1429,7 +1429,7 @@ FullO3CPU<Impl>::setVecPredReg(PhysRegIdPtr phys_reg,
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
+FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, RegVal val)
 {
     ccRegfileWrites++;
     regFile.setCCReg(phys_reg, val);
@@ -1508,7 +1508,7 @@ FullO3CPU<Impl>::getWritableArchVecPredReg(int reg_idx, ThreadID tid)
 }
 
 template <class Impl>
-CCReg
+RegVal
 FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
 {
     ccRegfileReads++;
@@ -1572,7 +1572,7 @@ FullO3CPU<Impl>::setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
+FullO3CPU<Impl>::setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
 {
     ccRegfileWrites++;
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 9612b3667..aabac5fea 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -463,7 +463,7 @@ class FullO3CPU : public BaseO3CPU
 
     VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
 
-    TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);
+    RegVal readCCReg(PhysRegIdPtr phys_reg);
 
     void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
 
@@ -475,7 +475,7 @@ class FullO3CPU : public BaseO3CPU
 
     void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val);
 
-    void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);
+    void setCCReg(PhysRegIdPtr phys_reg, RegVal val);
 
     RegVal readArchIntReg(int reg_idx, ThreadID tid);
 
@@ -514,7 +514,7 @@ class FullO3CPU : public BaseO3CPU
 
     VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid);
 
-    TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
+    RegVal readArchCCReg(int reg_idx, ThreadID tid);
 
     /** Architectural register accessors.  Looks up in the commit
      * rename table to obtain the true physical index of the
@@ -533,7 +533,7 @@ class FullO3CPU : public BaseO3CPU
     void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
                         const VecElem& val, ThreadID tid);
 
-    void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
+    void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);
 
     /** Sets the commit PC state of a specific thread. */
     void pcState(const TheISA::PCState &newPCState, ThreadID tid);
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index e6dffc81d..fc9abb92e 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -66,7 +66,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     /** Binary machine instruction type. */
     typedef TheISA::MachInst MachInst;
     /** Register types. */
-    typedef TheISA::CCReg   CCReg;
     using VecRegContainer = TheISA::VecRegContainer;
     using VecElem = TheISA::VecElem;
     static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
@@ -378,7 +377,8 @@ class BaseO3DynInst : public BaseDynInst<Impl>
         return this->cpu->getWritableVecPredReg(this->_destRegIdx[idx]);
     }
 
-    CCReg readCCRegOperand(const StaticInst *si, int idx)
+    RegVal
+    readCCRegOperand(const StaticInst *si, int idx)
     {
         return this->cpu->readCCReg(this->_srcRegIdx[idx]);
     }
@@ -424,7 +424,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
         BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val);
     }
 
-    void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
+    void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
     {
         this->cpu->setCCReg(this->_destRegIdx[idx], val);
         BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 163a13a25..d2fcd0749 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -65,7 +65,6 @@ class PhysRegFile
 {
   private:
 
-    typedef TheISA::CCReg CCReg;
     using VecElem = TheISA::VecElem;
     using VecRegContainer = TheISA::VecRegContainer;
     using PhysIds = std::vector<PhysRegId>;
@@ -95,7 +94,7 @@ class PhysRegFile
     std::vector<PhysRegId> vecPredRegIds;
 
     /** Condition-code register file. */
-    std::vector<CCReg> ccRegFile;
+    std::vector<RegVal> ccRegFile;
     std::vector<PhysRegId> ccRegIds;
 
     /** Misc Reg Ids */
@@ -290,7 +289,7 @@ class PhysRegFile
     }
 
     /** Reads a condition-code register. */
-    CCReg
+    RegVal
     readCCReg(PhysRegIdPtr phys_reg)
     {
         assert(phys_reg->isCCPhysReg());
@@ -365,7 +364,7 @@ class PhysRegFile
 
     /** Sets a condition-code register to the given value. */
     void
-    setCCReg(PhysRegIdPtr phys_reg, CCReg val)
+    setCCReg(PhysRegIdPtr phys_reg, RegVal val)
     {
         assert(phys_reg->isCCPhysReg());
 
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 1ab1a0876..5a05c0200 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -271,7 +271,9 @@ class O3ThreadContext : public ThreadContext
         return getWritableVecPredRegFlat(flattenRegId(id).index());
     }
 
-    virtual CCReg readCCReg(int reg_idx) {
+    virtual RegVal
+    readCCReg(int reg_idx)
+    {
         return readCCRegFlat(flattenRegId(RegId(CCRegClass,
                                                  reg_idx)).index());
     }
@@ -310,7 +312,7 @@ class O3ThreadContext : public ThreadContext
     }
 
     virtual void
-    setCCReg(int reg_idx, CCReg val)
+    setCCReg(int reg_idx, RegVal val)
     {
         setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
     }
@@ -424,8 +426,8 @@ class O3ThreadContext : public ThreadContext
     virtual void setVecPredRegFlat(int idx,
                                    const VecPredRegContainer& val) override;
 
-    virtual CCReg readCCRegFlat(int idx);
-    virtual void setCCRegFlat(int idx, CCReg val);
+    virtual RegVal readCCRegFlat(int idx);
+    virtual void setCCRegFlat(int idx, RegVal val);
 };
 
 #endif
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 2f653fa04..473e2e28e 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -247,7 +247,7 @@ O3ThreadContext<Impl>::getWritableVecPredRegFlat(int reg_id)
 }
 
 template <class Impl>
-TheISA::CCReg
+RegVal
 O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
 {
     return cpu->readArchCCReg(reg_idx, thread->threadId());
@@ -301,7 +301,7 @@ O3ThreadContext<Impl>::setVecPredRegFlat(int reg_idx,
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
+O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, RegVal val)
 {
     cpu->setArchCCReg(reg_idx, val, thread->threadId());