diff options
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-11-27 15:48:22 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-12-11 15:07:52 +0000 |
| commit | c3bd8eb1214cbebbc92c7958b80aa06913bce3ba (patch) | |
| tree | 6df53d30662ba49d93a1b90e3bfd1826bdb6726e /src/cpu/o3 | |
| parent | f73caae20fed7b4500a724ac85c20b637ee353a1 (diff) | |
| download | gem5-c3bd8eb1214cbebbc92c7958b80aa06913bce3ba.tar.xz | |
cpu: Fix coding style (byteEnable->byte_enable)
Change-Id: I2206559c6c2a6e6a0452e9c7d9964792afa9f358
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23282
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/cpu/o3')
| -rw-r--r-- | src/cpu/o3/cpu.hh | 4 | ||||
| -rw-r--r-- | src/cpu/o3/lsq.hh | 12 | ||||
| -rw-r--r-- | src/cpu/o3/lsq_impl.hh | 6 |
3 files changed, 11 insertions, 11 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 7c0ea5166..a129fa13d 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -714,12 +714,12 @@ class FullO3CPU : public BaseO3CPU Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op = nullptr, - const std::vector<bool>& byteEnable = + const std::vector<bool>& byte_enable = std::vector<bool>()) { return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr, - flags, res, std::move(amo_op), byteEnable); + flags, res, std::move(amo_op), byte_enable); } /** CPU read function, forwards read to LSQ. */ diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index ca92790b8..6db005cb3 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -406,16 +406,16 @@ class LSQ */ void addRequest(Addr addr, unsigned size, - const std::vector<bool>& byteEnable) + const std::vector<bool>& byte_enable) { - if (byteEnable.empty() || - isAnyActiveElement(byteEnable.begin(), byteEnable.end())) { + if (byte_enable.empty() || + isAnyActiveElement(byte_enable.begin(), byte_enable.end())) { auto request = std::make_shared<Request>(_inst->getASID(), addr, size, _flags, _inst->masterId(), _inst->instAddr(), _inst->contextId(), std::move(_amo_op)); - if (!byteEnable.empty()) { - request->setByteEnable(byteEnable); + if (!byte_enable.empty()) { + request->setByteEnable(byte_enable); } _requests.push_back(request); } @@ -1040,7 +1040,7 @@ class LSQ Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, - const std::vector<bool>& byteEnable); + const std::vector<bool>& byte_enable); /** The CPU pointer. */ O3CPU *cpu; diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh index d7dc618a2..e85dcb96a 100644 --- a/src/cpu/o3/lsq_impl.hh +++ b/src/cpu/o3/lsq_impl.hh @@ -688,7 +688,7 @@ Fault LSQ<Impl>::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, - const std::vector<bool>& byteEnable) + const std::vector<bool>& byte_enable) { // This comming request can be either load, store or atomic. // Atomic request has a corresponding pointer to its atomic memory @@ -720,8 +720,8 @@ LSQ<Impl>::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data, size, flags, data, res, std::move(amo_op)); } assert(req); - if (!byteEnable.empty()) { - req->_byteEnable = byteEnable; + if (!byte_enable.empty()) { + req->_byteEnable = byte_enable; } inst->setRequest(); req->taskId(cpu->taskId()); |