diff options
| author | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2018-10-16 16:09:02 +0100 |
|---|---|---|
| committer | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2019-03-14 10:42:27 +0000 |
| commit | c4cc3145cd1eeed236b5cd3f7b2424bc0761878e (patch) | |
| tree | b38eab6f5f389dfc53c2cf74275a83bacd2e9b18 /src/cpu/op_class.hh | |
| parent | 91195ae7f637d1d4879cc3bf0860147333846e75 (diff) | |
| download | gem5-c4cc3145cd1eeed236b5cd3f7b2424bc0761878e.tar.xz | |
arch-arm,cpu: Add initial support for Arm SVE
This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.
Additional authors:
- Javier Setoain <javier.setoain@arm.com>
- Gabor Dozsa <gabor.dozsa@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>
Thanks to Pau Cabre for his contribution of bugfixes.
Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/op_class.hh')
| -rw-r--r-- | src/cpu/op_class.hh | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/cpu/op_class.hh b/src/cpu/op_class.hh index 1bb88e1cd..ab5bdf247 100644 --- a/src/cpu/op_class.hh +++ b/src/cpu/op_class.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010,2018 ARM Limited + * Copyright (c) 2010, 2017-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -73,7 +73,11 @@ static const OpClass SimdMultOp = Enums::SimdMult; static const OpClass SimdMultAccOp = Enums::SimdMultAcc; static const OpClass SimdShiftOp = Enums::SimdShift; static const OpClass SimdShiftAccOp = Enums::SimdShiftAcc; +static const OpClass SimdDivOp = Enums::SimdDiv; static const OpClass SimdSqrtOp = Enums::SimdSqrt; +static const OpClass SimdReduceAddOp = Enums::SimdReduceAdd; +static const OpClass SimdReduceAluOp = Enums::SimdReduceAlu; +static const OpClass SimdReduceCmpOp = Enums::SimdReduceCmp; static const OpClass SimdFloatAddOp = Enums::SimdFloatAdd; static const OpClass SimdFloatAluOp = Enums::SimdFloatAlu; static const OpClass SimdFloatCmpOp = Enums::SimdFloatCmp; @@ -83,6 +87,8 @@ static const OpClass SimdFloatMiscOp = Enums::SimdFloatMisc; static const OpClass SimdFloatMultOp = Enums::SimdFloatMult; static const OpClass SimdFloatMultAccOp = Enums::SimdFloatMultAcc; static const OpClass SimdFloatSqrtOp = Enums::SimdFloatSqrt; +static const OpClass SimdFloatReduceCmpOp = Enums::SimdFloatReduceCmp; +static const OpClass SimdFloatReduceAddOp = Enums::SimdFloatReduceAdd; static const OpClass SimdAesOp = Enums::SimdAes; static const OpClass SimdAesMixOp = Enums::SimdAesMix; static const OpClass SimdSha1HashOp = Enums::SimdSha1Hash; @@ -91,6 +97,7 @@ static const OpClass SimdSha256HashOp = Enums::SimdSha256Hash; static const OpClass SimdSha256Hash2Op = Enums::SimdSha256Hash2; static const OpClass SimdShaSigma2Op = Enums::SimdShaSigma2; static const OpClass SimdShaSigma3Op = Enums::SimdShaSigma3; +static const OpClass SimdPredAluOp = Enums::SimdPredAlu; static const OpClass MemReadOp = Enums::MemRead; static const OpClass MemWriteOp = Enums::MemWrite; static const OpClass FloatMemReadOp = Enums::FloatMemRead; |