Merge zizzer.eecs.umich.edu:/bk/newmem

into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

src/cpu/ozone/cpu_impl.hh:
    Hand merged

--HG--
extra : convert_revision : f8a5b0205bcb78c8f5e109f456fe7bca80a7abac

1 files changed, 14 insertions, 2 deletions

diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc
index e239b7a94..730158258 100644
--- a/src/cpu/ozone/cpu_builder.cc
+++ b/src/cpu/ozone/cpu_builder.cc
@@ -63,6 +63,7 @@ SimObjectParam<System *> system;
 Param<int> cpu_id;
 SimObjectParam<AlphaITB *> itb;
 SimObjectParam<AlphaDTB *> dtb;
+Param<Tick> profile;
 #else
 SimObjectVectorParam<Process *> workload;
 //SimObjectParam<PageTable *> page_table;
@@ -76,16 +77,18 @@ Param<Counter> max_insts_any_thread;
 Param<Counter> max_insts_all_threads;
 Param<Counter> max_loads_any_thread;
 Param<Counter> max_loads_all_threads;
+Param<Tick> progress_interval;
 
 //SimObjectParam<BaseCache *> icache;
 //SimObjectParam<BaseCache *> dcache;
 
 Param<unsigned> cachePorts;
 Param<unsigned> width;
+Param<unsigned> frontEndLatency;
 Param<unsigned> frontEndWidth;
+Param<unsigned> backEndLatency;
 Param<unsigned> backEndWidth;
 Param<unsigned> backEndSquashLatency;
-Param<unsigned> backEndLatency;
 Param<unsigned> maxInstBufferSize;
 Param<unsigned> numPhysicalRegs;
 Param<unsigned> maxOutstandingMemOps;
@@ -140,6 +143,7 @@ Param<unsigned> RASSize;
 
 Param<unsigned> LQEntries;
 Param<unsigned> SQEntries;
+Param<bool> lsqLimits;
 Param<unsigned> LFSTSize;
 Param<unsigned> SSITSize;
 
@@ -181,6 +185,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
     INIT_PARAM(cpu_id, "processor ID"),
     INIT_PARAM(itb, "Instruction translation buffer"),
     INIT_PARAM(dtb, "Data translation buffer"),
+    INIT_PARAM(profile, ""),
 #else
     INIT_PARAM(workload, "Processes to run"),
 //    INIT_PARAM(page_table, "Page table"),
@@ -204,16 +209,18 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
                     "Terminate when all threads have reached this load"
                     "count",
                     0),
+    INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
 
 //    INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
 //    INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
 
     INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
     INIT_PARAM_DFLT(width, "Width", 1),
+    INIT_PARAM_DFLT(frontEndLatency, "Front end latency", 1),
     INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
+    INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
     INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
     INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
-    INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
     INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
     INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
     INIT_PARAM_DFLT(maxOutstandingMemOps, "Maximum outstanding memory operations", 4),
@@ -274,6 +281,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
 
     INIT_PARAM(LQEntries, "Number of load queue entries"),
     INIT_PARAM(SQEntries, "Number of store queue entries"),
+    INIT_PARAM_DFLT(lsqLimits, "LSQ size limits dispatch", true),
     INIT_PARAM(LFSTSize, "Last fetched store table size"),
     INIT_PARAM(SSITSize, "Store set ID table size"),
 
@@ -336,6 +344,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
     params->cpu_id = cpu_id;
     params->itb = itb;
     params->dtb = dtb;
+    params->profile = profile;
 #else
     params->workload = workload;
 //    params->pTable = page_table;
@@ -347,6 +356,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
     params->max_insts_all_threads = max_insts_all_threads;
     params->max_loads_any_thread = max_loads_any_thread;
     params->max_loads_all_threads = max_loads_all_threads;
+    params->progress_interval = progress_interval;
 
     //
     // Caches
@@ -357,6 +367,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
 
     params->width = width;
     params->frontEndWidth = frontEndWidth;
+    params->frontEndLatency = frontEndLatency;
     params->backEndWidth = backEndWidth;
     params->backEndSquashLatency = backEndSquashLatency;
     params->backEndLatency = backEndLatency;
@@ -414,6 +425,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
 
     params->LQEntries = LQEntries;
     params->SQEntries = SQEntries;
+    params->lsqLimits = lsqLimits;
 
     params->SSITSize = SSITSize;
     params->LFSTSize = LFSTSize;