cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.

1 files changed, 19 insertions, 0 deletions

diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index fcab901cf..b4b49a55b 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -769,6 +770,13 @@ OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
 }
 
 template <class Impl>
+CCReg
+OzoneCPU<Impl>::OzoneTC::readCCReg(int reg_idx)
+{
+    return thread->renameTable[reg_idx]->readCCResult();
+}
+
+template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val)
 {
@@ -801,6 +809,17 @@ OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val)
 
 template <class Impl>
 void
+OzoneCPU<Impl>::OzoneTC::setCCReg(int reg_idx, CCReg val)
+{
+    thread->renameTable[reg_idx]->setCCResult(val);
+
+    if (!thread->noSquashFromTC) {
+        cpu->squashFromTC();
+    }
+}
+
+template <class Impl>
+void
 OzoneCPU<Impl>::OzoneTC::setPC(Addr val)
 {
     thread->PC = val;