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authorYasuko Eckert <yasuko.eckert@amd.com>2013-10-15 14:22:44 -0400
committerYasuko Eckert <yasuko.eckert@amd.com>2013-10-15 14:22:44 -0400
commit2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch)
tree040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/cpu/ozone/cpu_impl.hh
parent552622184752dc798bc81f9b0b395db68aee9511 (diff)
downloadgem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz
cpu: add a condition-code register class
Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
Diffstat (limited to 'src/cpu/ozone/cpu_impl.hh')
-rw-r--r--src/cpu/ozone/cpu_impl.hh19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index fcab901cf..b4b49a55b 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -769,6 +770,13 @@ OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
}
template <class Impl>
+CCReg
+OzoneCPU<Impl>::OzoneTC::readCCReg(int reg_idx)
+{
+ return thread->renameTable[reg_idx]->readCCResult();
+}
+
+template <class Impl>
void
OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val)
{
@@ -801,6 +809,17 @@ OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val)
template <class Impl>
void
+OzoneCPU<Impl>::OzoneTC::setCCReg(int reg_idx, CCReg val)
+{
+ thread->renameTable[reg_idx]->setCCResult(val);
+
+ if (!thread->noSquashFromTC) {
+ cpu->squashFromTC();
+ }
+}
+
+template <class Impl>
+void
OzoneCPU<Impl>::OzoneTC::setPC(Addr val)
{
thread->PC = val;