summaryrefslogtreecommitdiff
path: root/src/cpu/ozone/cpu_impl.hh
diff options
context:
space:
mode:
authorKevin Lim <ktlim@umich.edu>2006-10-02 11:58:09 -0400
committerKevin Lim <ktlim@umich.edu>2006-10-02 11:58:09 -0400
commit568fa11084413913c2917bb2981d22db5bb2f495 (patch)
tree1bd4f585f43b56563ae37ec776a1bcd14430370f /src/cpu/ozone/cpu_impl.hh
parent4ed184eadefb16627f2807cb3dc7886bb1b920d1 (diff)
downloadgem5-568fa11084413913c2917bb2981d22db5bb2f495.tar.xz
Updates to fix merge issues and bring almost everything up to working speed. Ozone CPU remains untested, but everything else compiles and runs.
src/arch/alpha/isa_traits.hh: This got changed to the wrong version by accident. src/cpu/base.cc: Fix up progress event to not schedule itself if the interval is set to 0. src/cpu/base.hh: Fix up the CPU Progress Event to not print itself if it's set to 0. Also remove stats_reset_inst (something I added to m5 but isn't necessary here). src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.hh: Remove float variable of instResult; it's always held within the double part now. src/cpu/checker/cpu_impl.hh: Use thread and not cpuXC. src/cpu/o3/alpha/cpu_builder.cc: src/cpu/o3/checker_builder.cc: src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu_builder.cc: src/python/m5/objects/BaseCPU.py: Remove stats_reset_inst. src/cpu/o3/commit_impl.hh: src/cpu/ozone/lw_back_end_impl.hh: Get TC, not XCProxy. src/cpu/o3/cpu.cc: Switch out updates from the version of m5 I have. Also remove serialize code that got added twice. src/cpu/o3/iew_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/thread_state.hh: Remove code that was added twice. src/cpu/o3/lsq_unit.hh: Add back in stats that got lost in the merge. src/cpu/o3/lsq_unit_impl.hh: Use proper method to get flags. Also wake CPU if we're coming back from a cache miss. src/cpu/o3/thread_context_impl.hh: src/cpu/o3/thread_state.hh: Support profiling. src/cpu/ozone/cpu.hh: Update to use proper typename. src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/dyn_inst_impl.hh: Updates for newmem. src/cpu/ozone/lw_lsq_impl.hh: Get flags correctly. src/cpu/ozone/thread_state.hh: Reorder constructor initialization, use tc. src/sim/pseudo_inst.cc: Allow for loading of symbol file. Be sure to use ThreadContext and not ExecContext. --HG-- extra : convert_revision : c5657f84155807475ab4a1e20d944bb6f0d79d94
Diffstat (limited to 'src/cpu/ozone/cpu_impl.hh')
-rw-r--r--src/cpu/ozone/cpu_impl.hh20
1 files changed, 12 insertions, 8 deletions
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 5c8b5001d..bf547bf94 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -35,6 +35,7 @@
#include "arch/isa_traits.hh" // For MachInst
#include "base/trace.hh"
#include "cpu/base.hh"
+#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/ozone/cpu.hh"
@@ -52,6 +53,7 @@
#include "base/callback.hh"
#include "cpu/profile.hh"
#include "kern/kernel_stats.hh"
+#include "mem/physical.hh"
#include "sim/faults.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
@@ -102,7 +104,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
_status = Idle;
if (p->checker) {
-
+#if USE_CHECKER
BaseCPU *temp_checker = p->checker;
checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
checker->setMemory(mem);
@@ -240,7 +242,7 @@ template <class Impl>
void
OzoneCPU<Impl>::switchOut()
{
- BaseCPU::switchOut(_sampler);
+ BaseCPU::switchOut();
switchCount = 0;
// Front end needs state from back end, so switch out the back end first.
backEnd->switchOut();
@@ -468,10 +470,10 @@ OzoneCPU<Impl>::serialize(std::ostream &os)
// Use SimpleThread's ability to checkpoint to make it easier to
// write out the registers. Also make this static so it doesn't
// get instantiated multiple times (causes a panic in statistics).
- static CPUExecContext temp;
+ static SimpleThread temp;
nameOut(os, csprintf("%s.xc.0", name()));
- temp.copyXC(thread.getXCProxy());
+ temp.copyTC(thread.getTC());
temp.serialize(os);
}
@@ -487,11 +489,11 @@ OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
// Use SimpleThread's ability to checkpoint to make it easier to
// read in the registers. Also make this static so it doesn't
// get instantiated multiple times (causes a panic in statistics).
- static CPUExecContext temp;
+ static SimpleThread temp;
- temp.copyXC(thread.getXCProxy());
+ temp.copyTC(thread.getTC());
temp.unserialize(cp, csprintf("%s.xc.0", section));
- thread.getXCProxy()->copyArchRegs(temp.getProxy());
+ thread.getTC()->copyArchRegs(temp.getTC());
}
template <class Impl>
@@ -746,11 +748,13 @@ OzoneCPU<Impl>::processInterrupts()
if (ipl && ipl > thread.readMiscReg(IPR_IPLR)) {
thread.setMiscReg(IPR_ISR, summary);
thread.setMiscReg(IPR_INTID, ipl);
+#if USE_CHECKER
// @todo: Make this more transparent
if (checker) {
checker->threadBase()->setMiscReg(IPR_ISR, summary);
checker->threadBase()->setMiscReg(IPR_INTID, ipl);
}
+#endif
Fault fault = new InterruptFault;
fault->invoke(thread.getTC());
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
@@ -872,7 +876,7 @@ OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
copyArchRegs(old_context);
setCpuId(old_context->readCpuId());
- thread->inst = old_context->getInst();
+ thread->setInst(old_context->getInst());
#if !FULL_SYSTEM
setFuncExeInst(old_context->readFuncExeInst());
#else