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authorAli Saidi <saidi@eecs.umich.edu>2007-03-07 15:04:31 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-03-07 15:04:31 -0500
commit689cab36c90b56b3c8a7cda16d758acdd89f9de1 (patch)
tree2f0115320e0a6cfd13e5b054baa0ca13d5655519 /src/cpu/ozone/dyn_inst_impl.hh
parent329db76e47c825d4ecbe0f5251dbcfaf2ec09516 (diff)
downloadgem5-689cab36c90b56b3c8a7cda16d758acdd89f9de1.tar.xz
*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
--HG-- extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
Diffstat (limited to 'src/cpu/ozone/dyn_inst_impl.hh')
-rw-r--r--src/cpu/ozone/dyn_inst_impl.hh18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index 05a66d77a..8519917f5 100644
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -219,31 +219,31 @@ OzoneDynInst<Impl>::clearMemDependents()
template <class Impl>
TheISA::MiscReg
-OzoneDynInst<Impl>::readMiscReg(int misc_reg)
+OzoneDynInst<Impl>::readMiscRegNoEffect(int misc_reg)
{
- return this->thread->readMiscReg(misc_reg);
+ return this->thread->readMiscRegNoEffect(misc_reg);
}
template <class Impl>
TheISA::MiscReg
-OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg)
+OzoneDynInst<Impl>::readMiscReg(int misc_reg)
{
- return this->thread->readMiscRegWithEffect(misc_reg);
+ return this->thread->readMiscReg(misc_reg);
}
template <class Impl>
void
-OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
+OzoneDynInst<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
this->setIntResult(val);
- this->thread->setMiscReg(misc_reg, val);
+ this->thread->setMiscRegNoEffect(misc_reg, val);
}
template <class Impl>
void
-OzoneDynInst<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
{
- this->thread->setMiscRegWithEffect(misc_reg, val);
+ this->thread->setMiscReg(misc_reg, val);
}
#if FULL_SYSTEM
@@ -255,7 +255,7 @@ OzoneDynInst<Impl>::hwrei()
if (!(this->readPC() & 0x3))
return new AlphaISA::UnimplementedOpcodeFault;
- this->setNextPC(this->thread->readMiscReg(AlphaISA::IPR_EXC_ADDR));
+ this->setNextPC(this->thread->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
this->cpu->hwrei();