diff options
author | Kevin Lim <ktlim@umich.edu> | 2006-06-25 00:22:41 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-06-25 00:22:41 -0400 |
commit | 4787d357d51811bf5f4c73583e038de3f60e6a72 (patch) | |
tree | 63b5af6f5e29c67245e9781890292f344b5477bb /src/cpu/ozone/front_end.hh | |
parent | 63bdaeedfae71aa9eab4716a884fad9d7c4ece54 (diff) | |
download | gem5-4787d357d51811bf5f4c73583e038de3f60e6a72.tar.xz |
Make OzoneCPU work again in SE/FS.
src/cpu/ozone/cpu.hh:
Fixes to get OzoneCPU working in SE/FS again.
src/cpu/ozone/cpu_impl.hh:
Be sure to set up ports properly.
src/cpu/ozone/front_end.hh:
Allow port to be created without specifying its name at the beginning.
src/cpu/ozone/front_end_impl.hh:
Setup port properly, also only use checker if it's enabled.
src/cpu/ozone/lw_back_end_impl.hh:
Be sure to initialize variables.
src/cpu/ozone/lw_lsq.hh:
Handle locked flag for UP systems.
src/cpu/ozone/lw_lsq_impl.hh:
Initialize all variables.
src/python/m5/objects/OzoneCPU.py:
Fix up config.
--HG--
extra : convert_revision : c99e7bf82fc0dd1099c7a82eaebd58ab6017764d
Diffstat (limited to 'src/cpu/ozone/front_end.hh')
-rw-r--r-- | src/cpu/ozone/front_end.hh | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh index af310efc3..181609098 100644 --- a/src/cpu/ozone/front_end.hh +++ b/src/cpu/ozone/front_end.hh @@ -43,7 +43,7 @@ #include "sim/stats.hh" class ThreadContext; -class MemInterface; +class MemObject; template <class> class OzoneThreadState; class PageTable; @@ -75,7 +75,7 @@ class FrontEnd public: /** Default constructor. */ IcachePort(FrontEnd<Impl> *_fe) - : Port(_fe->name() + "-iport"), fe(_fe) + : fe(_fe) { } protected: @@ -105,8 +105,7 @@ class FrontEnd std::string name() const; - void setCPU(CPUType *cpu_ptr) - { cpu = cpu_ptr; } + void setCPU(CPUType *cpu_ptr); void setBackEnd(BackEnd *back_end_ptr) { backEnd = back_end_ptr; } @@ -206,6 +205,8 @@ class FrontEnd IcachePort icachePort; + MemObject *mem; + RequestPtr memReq; /** Mask to get a cache block's address. */ |