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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
| commit | d080581db1f9ee4e1e6d07d2b01c13c67908a391 (patch) | |
| tree | cc484b289fa5a30c4631f9faa1d8b456bffeebfc /src/cpu/ozone/front_end_impl.hh | |
| parent | 7a7c4c5fca83a8d47c7e71c9c080a882ebe204a9 (diff) | |
| parent | 639cb0a42d953ee32bc7e96b0cdfa96cd40e9fc1 (diff) | |
| download | gem5-d080581db1f9ee4e1e6d07d2b01c13c67908a391.tar.xz | |
Merge ARM into the head. ARM will compile but may not actually work.
Diffstat (limited to 'src/cpu/ozone/front_end_impl.hh')
| -rw-r--r-- | src/cpu/ozone/front_end_impl.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index 198ce0308..6b47ef539 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -477,10 +477,10 @@ FrontEnd<Impl>::fetchCacheLine() // Setup the memReq to do a read of the first isntruction's address. // Set the appropriate read size and flags as well. memReq = new Request(0, fetch_PC, cacheBlkSize, 0, - PC, cpu->readCpuId(), 0); + PC, cpu->thread->contextId()); // Translate the instruction request. - fault = cpu->translateInstReq(memReq, thread); + fault = cpu->itb->translateAtomic(memReq, thread); // Now do the timing access to see whether or not the instruction // exists within the cache. |