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author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:15:44 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:15:44 -0800 |
commit | 5605079b1f20bc7f6a4a80c8d1e4daabe7125270 (patch) | |
tree | 29dfa1685e3e257e3857ef7f9672778d43582440 /src/cpu/ozone/inorder_back_end.hh | |
parent | a1aba01a02a8c1261120de83d8fbfd6624f0cb17 (diff) | |
download | gem5-5605079b1f20bc7f6a4a80c8d1e4daabe7125270.tar.xz |
ISA: Replace the translate functions in the TLBs with translateAtomic.
Diffstat (limited to 'src/cpu/ozone/inorder_back_end.hh')
-rw-r--r-- | src/cpu/ozone/inorder_back_end.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh index 8850fa737..0840591e0 100644 --- a/src/cpu/ozone/inorder_back_end.hh +++ b/src/cpu/ozone/inorder_back_end.hh @@ -204,7 +204,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags) memReq->reset(addr, sizeof(T), flags); // translate to physical address - Fault fault = cpu->dtb->translate(memReq, thread->getTC(), false); + Fault fault = cpu->dtb->translateAtomic(memReq, thread->getTC(), false); // if we have a cache, do cache access too if (fault == NoFault && dcacheInterface) { @@ -245,7 +245,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) memReq->reset(addr, sizeof(T), flags); // translate to physical address - Fault fault = cpu->dtb->translate(memReq, thread->getTC(), true); + Fault fault = cpu->dtb->translateAtomic(memReq, thread->getTC(), true); if (fault == NoFault && dcacheInterface) { memReq->cmd = Write; |