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authorSteve Reinhardt <stever@eecs.umich.edu>2006-12-12 02:21:03 -0500
committerSteve Reinhardt <stever@eecs.umich.edu>2006-12-12 02:21:03 -0500
commitcdc3e5bc22369166eb4c616e8512324d60b6a20e (patch)
tree88c881a70fcbda63a50f90d06186ad8e0684f78e /src/cpu/ozone/inorder_back_end.hh
parent34924ce3b82ec19322990c721369b08ddfd3df8a (diff)
downloadgem5-cdc3e5bc22369166eb4c616e8512324d60b6a20e.tar.xz
Get rid of unused lock code.
--HG-- extra : convert_revision : a8030132268662ca54f487b8d32d09ba224317a8
Diffstat (limited to 'src/cpu/ozone/inorder_back_end.hh')
-rw-r--r--src/cpu/ozone/inorder_back_end.hh74
1 files changed, 0 insertions, 74 deletions
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index b2522bdc8..4fd8e02f8 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -236,25 +236,6 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
*/
return fault;
}
-#if 0
-template <class Impl>
-template <class T>
-Fault
-InorderBackEnd<Impl>::read(MemReqPtr &req, T &data)
-{
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
- if (req->isLocked()) {
- req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
- req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
- }
-#endif
-
- Fault error;
- error = thread->mem->read(req, data);
- data = LittleEndianGuest::gtoh(data);
- return error;
-}
-#endif
template <class Impl>
template <class T>
@@ -296,61 +277,6 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
*/
return fault;
}
-#if 0
-template <class Impl>
-template <class T>
-Fault
-InorderBackEnd<Impl>::write(MemReqPtr &req, T &data)
-{
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
- ExecContext *xc;
-
- // If this is a store conditional, act appropriately
- if (req->isLocked()) {
- xc = req->xc;
-
- if (req->isUncacheable()) {
- // Don't update result register (see stq_c in isa_desc)
- req->result = 2;
- xc->setStCondFailures(0);//Needed? [RGD]
- } else {
- bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
- Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
- req->result = lock_flag;
- if (!lock_flag ||
- ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- xc->setStCondFailures(xc->readStCondFailures() + 1);
- if (((xc->readStCondFailures()) % 100000) == 0) {
- std::cerr << "Warning: "
- << xc->readStCondFailures()
- << " consecutive store conditional failures "
- << "on cpu " << req->xc->readCpuId()
- << std::endl;
- }
- return NoFault;
- }
- else xc->setStCondFailures(0);
- }
- }
-
- // Need to clear any locked flags on other proccessors for
- // this address. Only do this for succsful Store Conditionals
- // and all other stores (WH64?). Unsuccessful Store
- // Conditionals would have returned above, and wouldn't fall
- // through.
- for (int i = 0; i < cpu->system->execContexts.size(); i++){
- xc = cpu->system->execContexts[i];
- if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
- (req->paddr & ~0xf)) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- }
- }
-
-#endif
- return thread->mem->write(req, (T)LittleEndianGuest::htog(data));
-}
-#endif
template <class Impl>
template <class T>