diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:15:34 -0800 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:15:34 -0800 |
commit | a1aba01a02a8c1261120de83d8fbfd6624f0cb17 (patch) | |
tree | 9d5e0abec98c0879b03a4d34d0862731424408f5 /src/cpu/ozone/inorder_back_end.hh | |
parent | f3090e5b704a2b7a02a736ec8601cd961fe3a865 (diff) | |
download | gem5-a1aba01a02a8c1261120de83d8fbfd6624f0cb17.tar.xz |
CPU: Get rid of translate... functions from various interface classes.
Diffstat (limited to 'src/cpu/ozone/inorder_back_end.hh')
-rw-r--r-- | src/cpu/ozone/inorder_back_end.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh index c23d801ba..8850fa737 100644 --- a/src/cpu/ozone/inorder_back_end.hh +++ b/src/cpu/ozone/inorder_back_end.hh @@ -204,7 +204,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags) memReq->reset(addr, sizeof(T), flags); // translate to physical address - Fault fault = cpu->translateDataReadReq(memReq); + Fault fault = cpu->dtb->translate(memReq, thread->getTC(), false); // if we have a cache, do cache access too if (fault == NoFault && dcacheInterface) { @@ -245,7 +245,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) memReq->reset(addr, sizeof(T), flags); // translate to physical address - Fault fault = cpu->translateDataWriteReq(memReq); + Fault fault = cpu->dtb->translate(memReq, thread->getTC(), true); if (fault == NoFault && dcacheInterface) { memReq->cmd = Write; |