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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 21:44:15 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 21:44:15 -0700 |
| commit | bd6f2bb538b09ce221c46d1ec5d5bfbf9a1d3350 (patch) | |
| tree | 5492dc138704c1c3da4592a42f6a45be904e0188 /src/cpu/ozone/lsq_unit_impl.hh | |
| parent | 089b3840865f816493a33f2ccf987307d0a79f87 (diff) | |
| download | gem5-bd6f2bb538b09ce221c46d1ec5d5bfbf9a1d3350.tar.xz | |
Mem: Change isLlsc to isLLSC.
Diffstat (limited to 'src/cpu/ozone/lsq_unit_impl.hh')
| -rw-r--r-- | src/cpu/ozone/lsq_unit_impl.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/ozone/lsq_unit_impl.hh b/src/cpu/ozone/lsq_unit_impl.hh index 7e7bbdb01..833aa0581 100644 --- a/src/cpu/ozone/lsq_unit_impl.hh +++ b/src/cpu/ozone/lsq_unit_impl.hh @@ -577,7 +577,7 @@ OzoneLSQ<Impl>::writebackStores() MemAccessResult result = dcacheInterface->access(req); //@todo temp fix for LL/SC (works fine for 1 CPU) - if (req->isLlsc()) { + if (req->isLLSC()) { req->result=1; panic("LL/SC! oh no no support!!!"); } @@ -596,7 +596,7 @@ OzoneLSQ<Impl>::writebackStores() Event *wb = NULL; /* typename IEW::LdWritebackEvent *wb = NULL; - if (req->isLlsc()) { + if (req->isLLSC()) { // Stx_C does not generate a system port transaction. req->result=0; wb = new typename IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst, @@ -630,7 +630,7 @@ OzoneLSQ<Impl>::writebackStores() // DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", // storeQueue[storeWBIdx].inst->seqNum); - if (req->isLlsc()) { + if (req->isLLSC()) { // Stx_C does not generate a system port transaction. req->result=1; typename BackEnd::LdWritebackEvent *wb = |