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author | Gabe Black <gblack@eecs.umich.edu> | 2011-11-18 01:33:28 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2011-11-18 01:33:28 -0800 |
commit | de21bb93ea4312a7e958698c634b16b10e02e21a (patch) | |
tree | c8aa7999dd0d5373c1de0d77eab7fd40f1d1a8fc /src/cpu/ozone/lw_back_end_impl.hh | |
parent | ec32d85f9dbd2354dea330deb4e984a43d4dbe5d (diff) | |
download | gem5-de21bb93ea4312a7e958698c634b16b10e02e21a.tar.xz |
SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
Diffstat (limited to 'src/cpu/ozone/lw_back_end_impl.hh')
-rw-r--r-- | src/cpu/ozone/lw_back_end_impl.hh | 53 |
1 files changed, 18 insertions, 35 deletions
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh index 880d0d183..c06a58754 100644 --- a/src/cpu/ozone/lw_back_end_impl.hh +++ b/src/cpu/ozone/lw_back_end_impl.hh @@ -520,7 +520,6 @@ LWBackEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm) fromCommit = comm->getWire(-1); } -#if FULL_SYSTEM template <class Impl> void LWBackEnd<Impl>::checkInterrupts() @@ -557,7 +556,6 @@ LWBackEnd<Impl>::checkInterrupts() } } } -#endif template <class Impl> void @@ -604,9 +602,7 @@ LWBackEnd<Impl>::tick() wbCycle = 0; -#if FULL_SYSTEM checkInterrupts(); -#endif if (trapSquash) { assert(!tcSquash); @@ -1049,16 +1045,8 @@ LWBackEnd<Impl>::commitInst(int inst_num) (inst->isStoreConditional() && inst->getFault() == NoFault) || inst->isMemBarrier() || inst->isWriteBarrier()) { -#if !FULL_SYSTEM - // Hack to make sure syscalls aren't executed until all stores - // write back their data. This direct communication shouldn't - // be used for anything other than this. - if (inst_num > 0 || LSQ.hasStoresToWB()) -#else if ((inst->isMemBarrier() || inst->isWriteBarrier() || - inst->isQuiesce()) && - LSQ.hasStoresToWB()) -#endif + inst->isQuiesce()) && LSQ.hasStoresToWB()) { DPRINTF(BE, "Waiting for all stores to writeback.\n"); return false; @@ -1184,11 +1172,7 @@ LWBackEnd<Impl>::commitInst(int inst_num) ++freed_regs; } -#if FULL_SYSTEM - if (thread->profile) { -// bool usermode = -// (xc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; -// thread->profilePC = usermode ? 1 : inst->readPC(); + if (FullSystem && thread->profile) { thread->profilePC = inst->readPC(); ProfileNode *node = thread->profile->consume(thread->getTC(), inst->staticInst); @@ -1196,7 +1180,6 @@ LWBackEnd<Impl>::commitInst(int inst_num) if (node) thread->profileNode = node; } -#endif if (inst->traceData) { inst->traceData->setFetchSeq(inst->seqNum); @@ -1225,23 +1208,23 @@ LWBackEnd<Impl>::commitInst(int inst_num) toIEW->doneSeqNum = inst->seqNum; lastCommitCycle = curTick(); -#if FULL_SYSTEM - int count = 0; - Addr oldpc; - do { - if (count == 0) - assert(!thread->inSyscall && !thread->trapPending); - oldpc = thread->readPC(); - cpu->system->pcEventQueue.service( - thread->getTC()); - count++; - } while (oldpc != thread->readPC()); - if (count > 1) { - DPRINTF(BE, "PC skip function event, stopping commit\n"); - tcSquash = true; - return false; + if (FullSystem) { + int count = 0; + Addr oldpc; + do { + if (count == 0) + assert(!thread->inSyscall && !thread->trapPending); + oldpc = thread->readPC(); + cpu->system->pcEventQueue.service( + thread->getTC()); + count++; + } while (oldpc != thread->readPC()); + if (count > 1) { + DPRINTF(BE, "PC skip function event, stopping commit\n"); + tcSquash = true; + return false; + } } -#endif return true; } |