Changes to get OzoneCPU to compile once more.

The changes largely are fixing up the memory accesses to use ports/Requests/Packets, supporting the splitting off of instantiation of template classes, and handling some of the reorganization that happened.

OzoneCPU is untested for now but at least compiles.  Fixes will be coming shortly.

SConstruct:
    Remove OzoneSimpleCPU from list of CPUs.
src/cpu/SConscript:
    Leave out OzoneSimpleCPU.
src/cpu/ozone/bpred_unit.cc:
    Fixes to get OzoneCPU to compile.
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/dyn_inst.hh:
src/cpu/ozone/dyn_inst_impl.hh:
src/cpu/ozone/front_end.cc:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/ozone_impl.hh:
src/cpu/ozone/rename_table.cc:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
    Fixes to get OzoneCPU back to compiling.

--HG--
extra : convert_revision : 90ffb397263bcf9fea3987317272c64f2b20f7e6

1 files changed, 26 insertions, 96 deletions

diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index ed406d5a3..dcd7a0d7e 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -28,9 +28,14 @@
  * Authors: Kevin Lim
  */
 
-#include "cpu/checker/cpu.hh"
+#include "config/use_checker.hh"
+
 #include "cpu/ozone/lw_back_end.hh"
-#include "encumbered/cpu/full/op_class.hh"
+#include "cpu/op_class.hh"
+
+#if USE_CHECKER
+#include "cpu/checker/cpu.hh"
+#endif
 
 template <class Impl>
 void
@@ -134,86 +139,11 @@ LWBackEnd<Impl>::replayMemInst(DynInstPtr &inst)
     assert(found_inst);
 }
 
-template<class Impl>
-LWBackEnd<Impl>::LdWritebackEvent::LdWritebackEvent(DynInstPtr &_inst,
-                                                  LWBackEnd<Impl> *_be)
-    : Event(&mainEventQueue), inst(_inst), be(_be), dcacheMiss(false)
-{
-    this->setFlags(Event::AutoDelete);
-}
-
-template<class Impl>
-void
-LWBackEnd<Impl>::LdWritebackEvent::process()
-{
-    DPRINTF(BE, "Load writeback event [sn:%lli]\n", inst->seqNum);
-//    DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum);
-
-    //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
-
-//    iewStage->wakeCPU();
-
-    if (be->isSwitchedOut())
-        return;
-
-    if (dcacheMiss) {
-        be->removeDcacheMiss(inst);
-    }
-
-    if (inst->isSquashed()) {
-        inst = NULL;
-        return;
-    }
-
-    if (!inst->isExecuted()) {
-        inst->setExecuted();
-
-        // Execute again to copy data to proper place.
-        inst->completeAcc();
-    }
-
-    // Need to insert instruction into queue to commit
-    be->instToCommit(inst);
-
-    //wroteToTimeBuffer = true;
-//    iewStage->activityThisCycle();
-
-    inst = NULL;
-}
-
-template<class Impl>
-const char *
-LWBackEnd<Impl>::LdWritebackEvent::description()
-{
-    return "Load writeback event";
-}
-
-
-template <class Impl>
-LWBackEnd<Impl>::DCacheCompletionEvent::DCacheCompletionEvent(LWBackEnd *_be)
-    : Event(&mainEventQueue, CPU_Tick_Pri), be(_be)
-{
-}
-
-template <class Impl>
-void
-LWBackEnd<Impl>::DCacheCompletionEvent::process()
-{
-}
-
-template <class Impl>
-const char *
-LWBackEnd<Impl>::DCacheCompletionEvent::description()
-{
-    return "Cache completion event";
-}
-
 template <class Impl>
 LWBackEnd<Impl>::LWBackEnd(Params *params)
     : d2i(5, 5), i2e(5, 5), e2c(5, 5), numInstsToWB(5, 5),
-      trapSquash(false), tcSquash(false), cacheCompletionEvent(this),
-      dcacheInterface(params->dcacheInterface), width(params->backEndWidth),
-      exactFullStall(true)
+      trapSquash(false), tcSquash(false),
+      width(params->backEndWidth), exactFullStall(true)
 {
     numROBEntries = params->numROBEntries;
     numInsts = 0;
@@ -569,7 +499,7 @@ LWBackEnd<Impl>::regStats()
 
 template <class Impl>
 void
-LWBackEnd<Impl>::setCPU(FullCPU *cpu_ptr)
+LWBackEnd<Impl>::setCPU(OzoneCPU *cpu_ptr)
 {
     cpu = cpu_ptr;
     LSQ.setCPU(cpu_ptr);
@@ -639,7 +569,7 @@ LWBackEnd<Impl>::handleFault(Fault &fault, Tick latency)
 
     // Consider holding onto the trap and waiting until the trap event
     // happens for this to be executed.
-    fault->invoke(thread->getTCProxy());
+    fault->invoke(thread->getTC());
 
     // Exit state update mode to avoid accidental updating.
     thread->inSyscall = false;
@@ -929,11 +859,6 @@ LWBackEnd<Impl>::executeInsts()
         // at the commit stage.
         if (inst->isMemRef() &&
             (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
-            if (dcacheInterface->isBlocked()) {
-                // Should I move the instruction aside?
-                DPRINTF(BE, "Execute: dcache is blocked\n");
-                break;
-            }
             DPRINTF(BE, "Execute: Initiating access for memory "
                     "reference.\n");
 
@@ -941,7 +866,7 @@ LWBackEnd<Impl>::executeInsts()
                 LSQ.executeLoad(inst);
             } else if (inst->isStore()) {
                 LSQ.executeStore(inst);
-                if (inst->req && !(inst->req->flags & LOCKED)) {
+                if (inst->req && !(inst->req->getFlags() & LOCKED)) {
                     inst->setExecuted();
 
                     instToCommit(inst);
@@ -1078,7 +1003,7 @@ LWBackEnd<Impl>::commitInst(int inst_num)
 
     thread->setPC(inst->readPC());
     thread->setNextPC(inst->readNextPC());
-    inst->reachedCommit = true;
+    inst->setAtCommit();
 
     // If the instruction is not executed yet, then it is a non-speculative
     // or store inst.  Signal backwards that it should be executed.
@@ -1183,9 +1108,11 @@ LWBackEnd<Impl>::commitInst(int inst_num)
 
     // Use checker prior to updating anything due to traps or PC
     // based events.
+#if USE_CHECKER
     if (checker) {
-        checker->tick(inst);
+        checker->verify(inst);
     }
+#endif
 
     if (inst_fault != NoFault) {
         DPRINTF(BE, "Inst [sn:%lli] PC %#x has a fault\n",
@@ -1200,9 +1127,12 @@ LWBackEnd<Impl>::commitInst(int inst_num)
         } else if (inst_num != 0) {
             DPRINTF(BE, "Will wait until instruction is head of commit group.\n");
             return false;
-        } else if (checker && inst->isStore()) {
-            checker->tick(inst);
         }
+#if USE_CHECKER
+        else if (checker && inst->isStore()) {
+            checker->verify(inst);
+        }
+#endif
 
         thread->setInst(
             static_cast<TheISA::MachInst>(inst->staticInst->machInst));
@@ -1259,7 +1189,7 @@ LWBackEnd<Impl>::commitInst(int inst_num)
             assert(!thread->inSyscall && !thread->trapPending);
         oldpc = thread->readPC();
         cpu->system->pcEventQueue.service(
-            thread->getTCProxy());
+            thread->getTC());
         count++;
     } while (oldpc != thread->readPC());
     if (count > 1) {
@@ -1346,7 +1276,7 @@ LWBackEnd<Impl>::squash(const InstSeqNum &sn)
 
         (*insts_it)->setCanCommit();
 
-        (*insts_it)->removeInROB();
+        (*insts_it)->clearInROB();
 
         for (int i = 0; i < (*insts_it)->numDestRegs(); ++i) {
             DynInstPtr prev_dest = (*insts_it)->getPrevDestInst(i);
@@ -1497,10 +1427,10 @@ LWBackEnd<Impl>::doSwitchOut()
 
 template <class Impl>
 void
-LWBackEnd<Impl>::takeOverFrom(ThreadContext *old_xc)
+LWBackEnd<Impl>::takeOverFrom(ThreadContext *old_tc)
 {
     switchedOut = false;
-    xcSquash = false;
+    tcSquash = false;
     trapSquash = false;
 
     numInsts = 0;
@@ -1510,7 +1440,7 @@ LWBackEnd<Impl>::takeOverFrom(ThreadContext *old_xc)
     switchedOut = false;
     dispatchStatus = Running;
     commitStatus = Running;
-    LSQ.takeOverFrom(old_xc);
+    LSQ.takeOverFrom(old_tc);
 }
 
 template <class Impl>