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| author | Nathan Binkert <nate@binkert.org> | 2008-10-21 07:12:53 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2008-10-21 07:12:53 -0700 |
| commit | 9836d81c2bba97e36c43ca22feee1d51a12ce6ac (patch) | |
| tree | eaa352df03cfe58d315e975bbe2a6384c801f221 /src/cpu/ozone/lw_back_end_impl.hh | |
| parent | aac93b7d0ce5e8e0241c7299b49cc59a9d095f3e (diff) | |
| download | gem5-9836d81c2bba97e36c43ca22feee1d51a12ce6ac.tar.xz | |
style: Use the correct m5 style for things relating to interrupts.
Diffstat (limited to 'src/cpu/ozone/lw_back_end_impl.hh')
| -rw-r--r-- | src/cpu/ozone/lw_back_end_impl.hh | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh index a5d79a789..60c42edd3 100644 --- a/src/cpu/ozone/lw_back_end_impl.hh +++ b/src/cpu/ozone/lw_back_end_impl.hh @@ -525,10 +525,7 @@ template <class Impl> void LWBackEnd<Impl>::checkInterrupts() { - if (cpu->checkInterrupts && - cpu->check_interrupts(tc) && - !trapSquash && - !tcSquash) { + if (cpu->checkInterrupts(tc) && !trapSquash && !tcSquash) { frontEnd->interruptPending = true; if (robEmpty() && !LSQ.hasStoresToWB()) { // Will need to squash all instructions currently in flight and have |