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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 21:44:15 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 21:44:15 -0700 |
| commit | bd6f2bb538b09ce221c46d1ec5d5bfbf9a1d3350 (patch) | |
| tree | 5492dc138704c1c3da4592a42f6a45be904e0188 /src/cpu/ozone/lw_lsq_impl.hh | |
| parent | 089b3840865f816493a33f2ccf987307d0a79f87 (diff) | |
| download | gem5-bd6f2bb538b09ce221c46d1ec5d5bfbf9a1d3350.tar.xz | |
Mem: Change isLlsc to isLLSC.
Diffstat (limited to 'src/cpu/ozone/lw_lsq_impl.hh')
| -rw-r--r-- | src/cpu/ozone/lw_lsq_impl.hh | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh index 3943dab2d..4d290a1e9 100644 --- a/src/cpu/ozone/lw_lsq_impl.hh +++ b/src/cpu/ozone/lw_lsq_impl.hh @@ -589,7 +589,7 @@ OzoneLWLSQ<Impl>::writebackStores() MemCmd command = req->isSwap() ? MemCmd::SwapReq : - (req->isLlsc() ? MemCmd::WriteReq : MemCmd::StoreCondReq); + (req->isLLSC() ? MemCmd::WriteReq : MemCmd::StoreCondReq); PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast); data_pkt->dataStatic(inst->memData); @@ -606,7 +606,7 @@ OzoneLWLSQ<Impl>::writebackStores() inst->seqNum); // @todo: Remove this SC hack once the memory system handles it. - if (req->isLlsc()) { + if (req->isLLSC()) { if (req->isUncacheable()) { req->setExtraData(2); } else { @@ -664,7 +664,7 @@ OzoneLWLSQ<Impl>::writebackStores() if (result != MA_HIT && dcacheInterface->doEvents()) { store_event->miss = true; typename BackEnd::LdWritebackEvent *wb = NULL; - if (req->isLlsc()) { + if (req->isLLSC()) { wb = new typename BackEnd::LdWritebackEvent(inst, be); store_event->wbEvent = wb; @@ -691,7 +691,7 @@ OzoneLWLSQ<Impl>::writebackStores() // DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", // inst->seqNum); - if (req->isLlsc()) { + if (req->isLLSC()) { // Stx_C does not generate a system port // transaction in the 21264, but that might be // hard to accomplish in this model. |