summaryrefslogtreecommitdiff
path: root/src/cpu/ozone/simple_params.hh
diff options
context:
space:
mode:
authorKevin Lim <ktlim@umich.edu>2006-06-22 23:33:26 -0400
committerKevin Lim <ktlim@umich.edu>2006-06-22 23:33:26 -0400
commit17f870f6d813df787baea116afb6f6af3897bc57 (patch)
treef02e351bcd433e69b841112ce05217ea44f2d81c /src/cpu/ozone/simple_params.hh
parente6c04b1584998ed2ea532da4070b356c75906f63 (diff)
downloadgem5-17f870f6d813df787baea116afb6f6af3897bc57.tar.xz
Changes to get OzoneCPU to compile once more.
The changes largely are fixing up the memory accesses to use ports/Requests/Packets, supporting the splitting off of instantiation of template classes, and handling some of the reorganization that happened. OzoneCPU is untested for now but at least compiles. Fixes will be coming shortly. SConstruct: Remove OzoneSimpleCPU from list of CPUs. src/cpu/SConscript: Leave out OzoneSimpleCPU. src/cpu/ozone/bpred_unit.cc: Fixes to get OzoneCPU to compile. src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu.cc: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_builder.cc: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/dyn_inst.hh: src/cpu/ozone/dyn_inst_impl.hh: src/cpu/ozone/front_end.cc: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/ozone_impl.hh: src/cpu/ozone/rename_table.cc: src/cpu/ozone/simple_params.hh: src/cpu/ozone/thread_state.hh: Fixes to get OzoneCPU back to compiling. --HG-- extra : convert_revision : 90ffb397263bcf9fea3987317272c64f2b20f7e6
Diffstat (limited to 'src/cpu/ozone/simple_params.hh')
-rw-r--r--src/cpu/ozone/simple_params.hh9
1 files changed, 4 insertions, 5 deletions
diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh
index 13eb05e77..11cee716f 100644
--- a/src/cpu/ozone/simple_params.hh
+++ b/src/cpu/ozone/simple_params.hh
@@ -37,8 +37,7 @@
class AlphaDTB;
class AlphaITB;
class FUPool;
-class FunctionalMemory;
-class MemInterface;
+class MemObject;
class PageTable;
class Process;
class System;
@@ -62,13 +61,13 @@ class SimpleParams : public BaseCPU::Params
//Page Table
PageTable *pTable;
- FunctionalMemory *mem;
+ MemObject *mem;
//
// Caches
//
- MemInterface *icacheInterface;
- MemInterface *dcacheInterface;
+// MemInterface *icacheInterface;
+// MemInterface *dcacheInterface;
unsigned cachePorts;
unsigned width;