O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes

the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.

4 files changed, 66 insertions, 0 deletions

diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index ee5e9e668..845cbbd95 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -507,6 +507,8 @@ class OzoneCPU : public BaseCPU
     void dumpInsts() { frontEnd->dumpInsts(); }
 
 #if FULL_SYSTEM
+    Fault hwrei();
+    bool simPalCheck(int palFunc);
     void processInterrupts();
 #else
     void syscall(uint64_t &callnum);
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 94af07525..c8e0dfe3d 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -669,6 +669,21 @@ OzoneCPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
 }
 #else
 template <class Impl>
+Fault
+OzoneCPU<Impl>::hwrei()
+{
+    // Need to move this to ISA code
+    // May also need to make this per thread
+
+    lockFlag = false;
+    lockAddrList.clear();
+    thread.kernelStats->hwrei();
+
+    // FIXME: XXX check for interrupts? XXX
+    return NoFault;
+}
+
+template <class Impl>
 void
 OzoneCPU<Impl>::processInterrupts()
 {
@@ -685,6 +700,31 @@ OzoneCPU<Impl>::processInterrupts()
         interrupt->invoke(thread.getTC());
     }
 }
+
+template <class Impl>
+bool
+OzoneCPU<Impl>::simPalCheck(int palFunc)
+{
+    // Need to move this to ISA code
+    // May also need to make this per thread
+    thread.kernelStats->callpal(palFunc, tc);
+
+    switch (palFunc) {
+      case PAL::halt:
+        haltContext(thread.readTid());
+        if (--System::numSystemsRunning == 0)
+            exitSimLoop("all cpus halted");
+        break;
+
+      case PAL::bpt:
+      case PAL::bugchk:
+        if (system->breakpoint())
+            return false;
+        break;
+    }
+
+    return true;
+}
 #endif
 
 template <class Impl>
diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index 12a19e70d..e138cbe13 100644
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -240,7 +240,9 @@ class OzoneDynInst : public BaseDynInst<Impl>
     void setMiscReg(int misc_reg, const MiscReg &val);
 
 #if FULL_SYSTEM
+    Fault hwrei();
     void trap(Fault fault);
+    bool simPalCheck(int palFunc);
 #else
     void syscall(uint64_t &callnum);
 #endif
diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index 396007687..8519917f5 100644
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -249,11 +249,33 @@ OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
 #if FULL_SYSTEM
 
 template <class Impl>
+Fault
+OzoneDynInst<Impl>::hwrei()
+{
+    if (!(this->readPC() & 0x3))
+        return new AlphaISA::UnimplementedOpcodeFault;
+
+    this->setNextPC(this->thread->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
+
+    this->cpu->hwrei();
+
+    // FIXME: XXX check for interrupts? XXX
+    return NoFault;
+}
+
+template <class Impl>
 void
 OzoneDynInst<Impl>::trap(Fault fault)
 {
     fault->invoke(this->thread->getTC());
 }
+
+template <class Impl>
+bool
+OzoneDynInst<Impl>::simPalCheck(int palFunc)
+{
+    return this->cpu->simPalCheck(palFunc);
+}
 #else
 template <class Impl>
 void