Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.

configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    No need for mem parameter any more.
src/cpu/checker/cpu.cc:
    Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
    Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
    Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
    Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
    Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
    Remove memory parameter.

--HG--
extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3

9 files changed, 6 insertions, 35 deletions

diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 70ec1d101..28ff8e9ba 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -368,8 +368,6 @@ class OzoneCPU : public BaseCPU
 
     virtual Port *getPort(const std::string &name, int idx);
 
-    MemObject *mem;
-
     FrontEnd *frontEnd;
 
     BackEnd *backEnd;
diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc
index 730158258..39be9fd74 100644
--- a/src/cpu/ozone/cpu_builder.cc
+++ b/src/cpu/ozone/cpu_builder.cc
@@ -69,8 +69,6 @@ SimObjectVectorParam<Process *> workload;
 //SimObjectParam<PageTable *> page_table;
 #endif // FULL_SYSTEM
 
-SimObjectParam<MemObject *> mem;
-
 SimObjectParam<BaseCPU *> checker;
 
 Param<Counter> max_insts_any_thread;
@@ -191,8 +189,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
 //    INIT_PARAM(page_table, "Page table"),
 #endif // FULL_SYSTEM
 
-    INIT_PARAM_DFLT(mem, "Memory", NULL),
-
     INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
 
     INIT_PARAM_DFLT(max_insts_any_thread,
@@ -350,7 +346,6 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
 //    params->pTable = page_table;
 #endif // FULL_SYSTEM
 
-    params->mem = mem;
     params->checker = checker;
     params->max_insts_any_thread = max_insts_any_thread;
     params->max_insts_all_threads = max_insts_all_threads;
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index bf547bf94..685bf3cb4 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -93,10 +93,10 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
 #if FULL_SYSTEM
     : BaseCPU(p), thread(this, 0), tickEvent(this, p->width),
 #else
-    : BaseCPU(p), thread(this, 0, p->workload[0], 0, p->mem),
+    : BaseCPU(p), thread(this, 0, p->workload[0], 0),
       tickEvent(this, p->width),
 #endif
-      mem(p->mem), comm(5, 5)
+      comm(5, 5)
 {
     frontEnd = new FrontEnd(p);
     backEnd = new BackEnd(p);
@@ -107,7 +107,6 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
 #if USE_CHECKER
         BaseCPU *temp_checker = p->checker;
         checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
-        checker->setMemory(mem);
 #if FULL_SYSTEM
         checker->setSystem(p->system);
 #endif
@@ -198,19 +197,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
     frontEnd->renameTable.copyFrom(thread.renameTable);
     backEnd->renameTable.copyFrom(thread.renameTable);
 
-#if !FULL_SYSTEM
-    /* Use this port to for syscall emulation writes to memory. */
-    Port *mem_port;
-    TranslatingPort *trans_port;
-    trans_port = new TranslatingPort(csprintf("%s-%d-funcport",
-                                              name(), 0),
-                                     p->workload[0]->pTable,
-                                     false);
-    mem_port = p->mem->getPort("functional");
-    mem_port->setPeer(trans_port);
-    trans_port->setPeer(mem_port);
-    thread.setMemPort(trans_port);
-#else
+#if FULL_SYSTEM
     Port *mem_port;
     FunctionalPort *phys_port;
     VirtualPort *virt_port;
diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh
index 2bdca35b9..e09e4de9c 100644
--- a/src/cpu/ozone/front_end.hh
+++ b/src/cpu/ozone/front_end.hh
@@ -208,8 +208,6 @@ class FrontEnd
 
     IcachePort icachePort;
 
-    MemObject *mem;
-
     RequestPtr memReq;
 
     /** Mask to get a cache block's address. */
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 36e87ec9c..b8fce4292 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -91,7 +91,6 @@ template <class Impl>
 FrontEnd<Impl>::FrontEnd(Params *params)
     : branchPred(params),
       icachePort(this),
-      mem(params->mem),
       numInstsReady(params->frontEndLatency, 0),
       instBufferSize(0),
       maxInstBufferSize(params->maxInstBufferSize),
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index dc58a8285..7e6849668 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -239,8 +239,6 @@ class OzoneLWLSQ {
     /** Pointer to the back-end stage. */
     BackEnd *be;
 
-    MemObject *mem;
-
     class DcachePort : public Port
     {
       protected:
diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh
index 1f3f18502..ee1968626 100644
--- a/src/cpu/ozone/lw_lsq_impl.hh
+++ b/src/cpu/ozone/lw_lsq_impl.hh
@@ -154,8 +154,6 @@ OzoneLWLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
         SQIndices.push(i);
     }
 
-    mem = params->mem;
-
     usedPorts = 0;
     cachePorts = params->cachePorts;
 
diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh
index 3f63d2e1d..3e554c812 100644
--- a/src/cpu/ozone/simple_params.hh
+++ b/src/cpu/ozone/simple_params.hh
@@ -61,8 +61,6 @@ class SimpleParams : public BaseCPU::Params
     //Page Table
     PageTable *pTable;
 
-    MemObject *mem;
-
     //
     // Caches
     //
diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index c86f3552e..c226d7502 100644
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -67,7 +67,7 @@ struct OzoneThreadState : public ThreadState {
 
 #if FULL_SYSTEM
     OzoneThreadState(CPUType *_cpu, int _thread_num)
-        : ThreadState(-1, _thread_num),
+        : ThreadState(_cpu, -1, _thread_num),
           intrflag(0), cpu(_cpu), inSyscall(0), trapPending(0)
     {
         if (cpu->params->profile) {
@@ -87,8 +87,8 @@ struct OzoneThreadState : public ThreadState {
     }
 #else
     OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process,
-                     int _asid, MemObject *mem)
-        : ThreadState(-1, _thread_num, _process, _asid, mem),
+                     int _asid)
+        : ThreadState(_cpu, -1, _thread_num, _process, _asid),
           cpu(_cpu), inSyscall(0), trapPending(0)
     {
         miscRegFile.clear();