Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults

--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675

9 files changed, 42 insertions, 42 deletions

diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc
index b4c4686b7..9ad1e639f 100644
--- a/src/cpu/ozone/checker_builder.cc
+++ b/src/cpu/ozone/checker_builder.cc
@@ -68,8 +68,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
     Param<Tick> progress_interval;
 
 #if FULL_SYSTEM
-    SimObjectParam<AlphaITB *> itb;
-    SimObjectParam<AlphaDTB *> dtb;
+    SimObjectParam<TheISA::ITB *> itb;
+    SimObjectParam<TheISA::DTB *> dtb;
     SimObjectParam<System *> system;
     Param<int> cpu_id;
     Param<Tick> profile;
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index bd46b198b..14c32620b 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -51,8 +51,11 @@
 #if FULL_SYSTEM
 #include "arch/alpha/tlb.hh"
 
-class AlphaITB;
-class AlphaDTB;
+namespace TheISA
+{
+    class ITB;
+    class DTB;
+}
 class PhysicalMemory;
 class MemoryController;
 
@@ -120,9 +123,9 @@ class OzoneCPU : public BaseCPU
 
         PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
 
-        AlphaITB *getITBPtr() { return cpu->itb; }
+        TheISA::ITB *getITBPtr() { return cpu->itb; }
 
-        AlphaDTB * getDTBPtr() { return cpu->dtb; }
+        TheISA::DTB * getDTBPtr() { return cpu->dtb; }
 
         Kernel::Statistics *getKernelStats()
         { return thread->getKernelStats(); }
@@ -224,11 +227,11 @@ class OzoneCPU : public BaseCPU
         // ISA stuff:
         MiscReg readMiscReg(int misc_reg);
 
-        MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
+        MiscReg readMiscRegWithEffect(int misc_reg);
 
-        Fault setMiscReg(int misc_reg, const MiscReg &val);
+        void setMiscReg(int misc_reg, const MiscReg &val);
 
-        Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+        void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
 
         unsigned readStCondFailures()
         { return thread->storeCondFailures; }
diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc
index 730158258..8a572ba38 100644
--- a/src/cpu/ozone/cpu_builder.cc
+++ b/src/cpu/ozone/cpu_builder.cc
@@ -61,8 +61,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
 #if FULL_SYSTEM
 SimObjectParam<System *> system;
 Param<int> cpu_id;
-SimObjectParam<AlphaITB *> itb;
-SimObjectParam<AlphaDTB *> dtb;
+SimObjectParam<TheISA::ITB *> itb;
+SimObjectParam<TheISA::DTB *> dtb;
 Param<Tick> profile;
 #else
 SimObjectVectorParam<Process *> workload;
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index bf547bf94..b34b061d9 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -1156,37 +1156,31 @@ OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
 
 template <class Impl>
 TheISA::MiscReg
-OzoneCPU<Impl>::OzoneTC::readMiscRegWithEffect(int misc_reg, Fault &fault)
+OzoneCPU<Impl>::OzoneTC::readMiscRegWithEffect(int misc_reg)
 {
-    return thread->miscRegFile.readRegWithEffect(misc_reg,
-                                                 fault, this);
+    return thread->miscRegFile.readRegWithEffect(misc_reg, this);
 }
 
 template <class Impl>
-Fault
+void
 OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
 {
     // Needs to setup a squash event unless we're in syscall mode
-    Fault ret_fault = thread->miscRegFile.setReg(misc_reg, val);
+    thread->miscRegFile.setReg(misc_reg, val);
 
     if (!thread->inSyscall) {
         cpu->squashFromTC();
     }
-
-    return ret_fault;
 }
 
 template <class Impl>
-Fault
+void
 OzoneCPU<Impl>::OzoneTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
 {
     // Needs to setup a squash event unless we're in syscall mode
-    Fault ret_fault = thread->miscRegFile.setRegWithEffect(misc_reg, val,
-                                                           this);
+    thread->miscRegFile.setRegWithEffect(misc_reg, val, this);
 
     if (!thread->inSyscall) {
         cpu->squashFromTC();
     }
-
-    return ret_fault;
 }
diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index d3871568a..532317b08 100644
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -230,11 +230,11 @@ class OzoneDynInst : public BaseDynInst<Impl>
     // ISA stuff
     MiscReg readMiscReg(int misc_reg);
 
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
+    MiscReg readMiscRegWithEffect(int misc_reg);
 
-    Fault setMiscReg(int misc_reg, const MiscReg &val);
+    void setMiscReg(int misc_reg, const MiscReg &val);
 
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
 
 #if FULL_SYSTEM
     Fault hwrei();
diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index d86f2dc8b..68736ae61 100644
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -223,24 +223,24 @@ OzoneDynInst<Impl>::readMiscReg(int misc_reg)
 
 template <class Impl>
 TheISA::MiscReg
-OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault)
+OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg)
 {
-    return this->thread->readMiscRegWithEffect(misc_reg, fault);
+    return this->thread->readMiscRegWithEffect(misc_reg);
 }
 
 template <class Impl>
-Fault
+void
 OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
 {
     this->setIntResult(val);
-    return this->thread->setMiscReg(misc_reg, val);
+    this->thread->setMiscReg(misc_reg, val);
 }
 
 template <class Impl>
-Fault
+void
 OzoneDynInst<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
 {
-    return this->thread->setMiscRegWithEffect(misc_reg, val);
+    this->thread->setMiscRegWithEffect(misc_reg, val);
 }
 
 #if FULL_SYSTEM
diff --git a/src/cpu/ozone/simple_cpu_builder.cc b/src/cpu/ozone/simple_cpu_builder.cc
index baaf7c708..e7214d2ba 100644
--- a/src/cpu/ozone/simple_cpu_builder.cc
+++ b/src/cpu/ozone/simple_cpu_builder.cc
@@ -64,8 +64,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
 #if FULL_SYSTEM
 SimObjectParam<System *> system;
 Param<int> cpu_id;
-SimObjectParam<AlphaITB *> itb;
-SimObjectParam<AlphaDTB *> dtb;
+SimObjectParam<TheISA::ITB *> itb;
+SimObjectParam<TheISA::DTB *> dtb;
 #else
 SimObjectVectorParam<Process *> workload;
 //SimObjectParam<PageTable *> page_table;
diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh
index 3f63d2e1d..3473b088c 100644
--- a/src/cpu/ozone/simple_params.hh
+++ b/src/cpu/ozone/simple_params.hh
@@ -34,8 +34,11 @@
 #include "cpu/ozone/cpu.hh"
 
 //Forward declarations
-class AlphaDTB;
-class AlphaITB;
+namespace TheISA
+{
+    class DTB;
+    class ITB;
+}
 class FUPool;
 class MemObject;
 class PageTable;
@@ -53,7 +56,7 @@ class SimpleParams : public BaseCPU::Params
   public:
 
 #if FULL_SYSTEM
-    AlphaITB *itb; AlphaDTB *dtb;
+    TheISA::ITB *itb; TheISA::DTB *dtb;
 #else
     std::vector<Process *> workload;
 #endif // FULL_SYSTEM
diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index 985e09b52..ec51251b7 100644
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -120,19 +120,19 @@ struct OzoneThreadState : public ThreadState {
         return miscRegFile.readReg(misc_reg);
     }
 
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+    MiscReg readMiscRegWithEffect(int misc_reg)
     {
         return miscRegFile.readRegWithEffect(misc_reg, fault, tc);
     }
 
-    Fault setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
-        return miscRegFile.setReg(misc_reg, val);
+        miscRegFile.setReg(misc_reg, val);
     }
 
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
-        return miscRegFile.setRegWithEffect(misc_reg, val, tc);
+        miscRegFile.setRegWithEffect(misc_reg, val, tc);
     }
 
     uint64_t readPC()