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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-08-01 22:50:14 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-08-01 22:50:14 -0700 |
| commit | a13a706a207296b40dbe43576fad423cf5f4679a (patch) | |
| tree | 119bd1bd09542130d603c8f30c0494313180753a /src/cpu/ozone | |
| parent | 1c2800465480993040e3058ef94ce30efbe982ec (diff) | |
| download | gem5-a13a706a207296b40dbe43576fad423cf5f4679a.tar.xz | |
Fix setting of INST_FETCH flag for O3 CPU.
It's still broken in inorder.
Also enhance DPRINTFs in cache and physical memory so we
can see more easily whether it's getting set or not.
Diffstat (limited to 'src/cpu/ozone')
| -rw-r--r-- | src/cpu/ozone/inorder_back_end.hh | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh index dd9e23f97..f242645a2 100644 --- a/src/cpu/ozone/inorder_back_end.hh +++ b/src/cpu/ozone/inorder_back_end.hh @@ -211,7 +211,6 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags) memReq->cmd = Read; memReq->completionEvent = NULL; memReq->time = curTick; - memReq->flags &= ~INST_FETCH; MemAccessResult result = dcacheInterface->access(memReq); // Ugly hack to get an event scheduled *only* if the access is @@ -252,7 +251,6 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) // memcpy(memReq->data,(uint8_t *)&data,memReq->size); memReq->completionEvent = NULL; memReq->time = curTick; - memReq->flags &= ~INST_FETCH; MemAccessResult result = dcacheInterface->access(memReq); // Ugly hack to get an event scheduled *only* if the access is @@ -293,7 +291,6 @@ InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx) req->time = curTick; assert(!req->data); req->data = new uint8_t[64]; - req->flags &= ~INST_FETCH; Fault fault = cpu->read(req, data); memcpy(req->data, &data, sizeof(T)); @@ -363,7 +360,6 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx) memcpy(req->data,(uint8_t *)&data,req->size); req->completionEvent = NULL; req->time = curTick; - req->flags &= ~INST_FETCH; MemAccessResult result = dcacheInterface->access(req); // Ugly hack to get an event scheduled *only* if the access is |