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authorAli Saidi <Ali.Saidi@ARM.com>2010-11-08 13:58:22 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2010-11-08 13:58:22 -0600
commitcdacbe734a9e6e0f20e0a37ef694995373b83f66 (patch)
tree775ea93dcd7acd5255818739ac78523634c8cc62 /src/cpu/ozone
parentf4f5d03ed211571f07f13ea9d5df0d70f3101aa3 (diff)
downloadgem5-cdacbe734a9e6e0f20e0a37ef694995373b83f66.tar.xz
ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
This change modifies the way prefetches work. They are now like normal loads that don't writeback a register. Previously prefetches were supposed to call prefetch() on the exection context, so they executed with execute() methods instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs are blank, meaning that they get executed, but don't actually do anything. On Alpha dead cache copy code was removed and prefetches are now normal ops. They count as executed operations, but still don't do anything and IsMemRef is not longer set on them. On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch instructions. The timing simple CPU doesn't try to do anything special for prefetches now and they execute with the normal memory code path.
Diffstat (limited to 'src/cpu/ozone')
-rw-r--r--src/cpu/ozone/cpu.hh14
-rw-r--r--src/cpu/ozone/cpu_impl.hh89
2 files changed, 0 insertions, 103 deletions
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index ad23b2790..05ff92289 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -409,20 +409,6 @@ class OzoneCPU : public BaseCPU
return backEnd->write(req, data, store_idx);
}
- void prefetch(Addr addr, unsigned flags)
- {
- // need to do this...
- }
-
- void writeHint(Addr addr, int size, unsigned flags)
- {
- // need to do this...
- }
-
- Fault copySrcTranslate(Addr src);
-
- Fault copy(Addr dest);
-
public:
void squashFromTC();
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 08da1724b..a22ada5d0 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -481,95 +481,6 @@ OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
thread.getTC()->copyArchRegs(temp.getTC());
}
-template <class Impl>
-Fault
-OzoneCPU<Impl>::copySrcTranslate(Addr src)
-{
- panic("Copy not implemented!\n");
- return NoFault;
-#if 0
- static bool no_warn = true;
- unsigned blk_size = dcacheInterface ? dcacheInterface->getBlockSize() : 64;
- // Only support block sizes of 64 atm.
- assert(blk_size == 64);
- int offset = src & (blk_size - 1);
-
- // Make sure block doesn't span page
- if (no_warn &&
- (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
- (src >> 40) != 0xfffffc) {
- warn("Copied block source spans pages %x.", src);
- no_warn = false;
- }
-
- memReq->reset(src & ~(blk_size - 1), blk_size);
-
- // translate to physical address
- Fault fault = tc->translateDataReadReq(memReq);
-
- assert(fault != Alignment_Fault);
-
- if (fault == NoFault) {
- tc->copySrcAddr = src;
- tc->copySrcPhysAddr = memReq->paddr + offset;
- } else {
- tc->copySrcAddr = 0;
- tc->copySrcPhysAddr = 0;
- }
- return fault;
-#endif
-}
-
-template <class Impl>
-Fault
-OzoneCPU<Impl>::copy(Addr dest)
-{
- panic("Copy not implemented!\n");
- return NoFault;
-#if 0
- static bool no_warn = true;
- unsigned blk_size = dcacheInterface ? dcacheInterface->getBlockSize() : 64;
- // Only support block sizes of 64 atm.
- assert(blk_size == 64);
- uint8_t data[blk_size];
- //assert(tc->copySrcAddr);
- int offset = dest & (blk_size - 1);
-
- // Make sure block doesn't span page
- if (no_warn &&
- (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
- (dest >> 40) != 0xfffffc) {
- no_warn = false;
- warn("Copied block destination spans pages %x. ", dest);
- }
-
- memReq->reset(dest & ~(blk_size -1), blk_size);
- // translate to physical address
- Fault fault = tc->translateDataWriteReq(memReq);
-
- assert(fault != Alignment_Fault);
-
- if (fault == NoFault) {
- Addr dest_addr = memReq->paddr + offset;
- // Need to read straight from memory since we have more than 8 bytes.
- memReq->paddr = tc->copySrcPhysAddr;
- tc->mem->read(memReq, data);
- memReq->paddr = dest_addr;
- tc->mem->write(memReq, data);
- if (dcacheInterface) {
- memReq->cmd = Copy;
- memReq->completionEvent = NULL;
- memReq->paddr = tc->copySrcPhysAddr;
- memReq->dest = dest_addr;
- memReq->size = 64;
- memReq->time = curTick;
- dcacheInterface->access(memReq);
- }
- }
- return fault;
-#endif
-}
-
#if FULL_SYSTEM
template <class Impl>
Addr