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| author | Pau Cabre <pau.cabre@metempsy.com> | 2018-11-09 00:30:15 +0100 |
|---|---|---|
| committer | Pau Cabre <pau.cabre@metempsy.com> | 2018-11-14 21:44:24 +0000 |
| commit | a4a5fa7fa591e91be86223f1fc8936d88255ac13 (patch) | |
| tree | d521d4fd4c45764e14e794e04ed7872fb15de33f /src/cpu/pred/BranchPredictor.py | |
| parent | d8bc7899a97b85600e2e7ba12f2aec3d42fefc66 (diff) | |
| download | gem5-a4a5fa7fa591e91be86223f1fc8936d88255ac13.tar.xz | |
cpu: Fixed ratio of pred to hyst bits for LTAGE Bimodal
The LTAGE paper states 1 hyst bit shared for 4 pred bits.
Made this ratio configurable use 4 by default.
Also changed the Bimodal structure to use two std::vector<bool> (one for
pred and one for hyst bits)
Change-Id: I6793e8e358be01b75b8fd181ddad50f259862d79
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14120
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/pred/BranchPredictor.py')
| -rw-r--r-- | src/cpu/pred/BranchPredictor.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/pred/BranchPredictor.py b/src/cpu/pred/BranchPredictor.py index 1b400c2b7..9f3516597 100644 --- a/src/cpu/pred/BranchPredictor.py +++ b/src/cpu/pred/BranchPredictor.py @@ -92,6 +92,9 @@ class LTAGE(BranchPredictor): cxx_header = "cpu/pred/ltage.hh" logSizeBiMP = Param.Unsigned(14, "Log size of Bimodal predictor in bits") + logRatioBiModalHystEntries = Param.Unsigned(2, + "Log num of prediction entries for a shared hysteresis bit " \ + "for the Bimodal") logSizeTagTables = Param.Unsigned(11, "Log size of tag table in LTAGE") logSizeLoopPred = Param.Unsigned(8, "Log size of the loop predictor") nHistoryTables = Param.Unsigned(12, "Number of history tables") |