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| author | Andrea Pellegrini <andrea.pellegrini@gmail.com> | 2013-01-22 00:13:28 -0600 |
|---|---|---|
| committer | Andrea Pellegrini <andrea.pellegrini@gmail.com> | 2013-01-22 00:13:28 -0600 |
| commit | 11d5ffa108983d5d9742f0aad23f80c691f285ee (patch) | |
| tree | 9396a4de982dd7441b5117389705acabcb7b0640 /src/cpu/pred/bpred_unit.cc | |
| parent | fc57ae640130c2d7610f4ff20a3d8816b88042bf (diff) | |
| download | gem5-11d5ffa108983d5d9742f0aad23f80c691f285ee.tar.xz | |
o3 cpu: fix zero reg problem
There was an issue w/ the rename logic, which would assign a previous physical
register to the ZeroReg architectural register in x86. This issue was giving
problems for instructions squashed in threads w/ ID different from 0,
sometimes allowing non-mispredicted instructions to obtain a value different
from zero when reading the zeroReg.
Diffstat (limited to 'src/cpu/pred/bpred_unit.cc')
0 files changed, 0 insertions, 0 deletions