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| author | Anthony Gutierrez <atgutier@umich.edu> | 2014-06-30 13:50:03 -0400 |
|---|---|---|
| committer | Anthony Gutierrez <atgutier@umich.edu> | 2014-06-30 13:50:03 -0400 |
| commit | f34a8f0d6163fe82849d494bf78c0f5ec175861c (patch) | |
| tree | b3133ce45f089479408e25b73347a14ead3c620f /src/cpu/pred/bpred_unit.hh | |
| parent | db267da8221ce4905e08e84967096d7a9fa23ca6 (diff) | |
| download | gem5-f34a8f0d6163fe82849d494bf78c0f5ec175861c.tar.xz | |
cpu: implement a bi-mode branch predictor
Diffstat (limited to 'src/cpu/pred/bpred_unit.hh')
| -rw-r--r-- | src/cpu/pred/bpred_unit.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/pred/bpred_unit.hh b/src/cpu/pred/bpred_unit.hh index 95f9a3573..0bc0d1569 100644 --- a/src/cpu/pred/bpred_unit.hh +++ b/src/cpu/pred/bpred_unit.hh @@ -90,8 +90,8 @@ class BPredUnit : public SimObject bool predict(StaticInstPtr &inst, const InstSeqNum &seqNum, TheISA::PCState &pc, ThreadID tid); bool predictInOrder(StaticInstPtr &inst, const InstSeqNum &seqNum, - int asid, TheISA::PCState &instPC, TheISA::PCState &predPC, - ThreadID tid); + int asid, TheISA::PCState &instPC, + TheISA::PCState &predPC, ThreadID tid); // @todo: Rename this function. virtual void uncondBranch(void * &bp_history) = 0; |