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| author | Pau Cabre <pau.cabre@metempsy.com> | 2018-11-09 00:30:15 +0100 |
|---|---|---|
| committer | Pau Cabre <pau.cabre@metempsy.com> | 2018-11-14 21:44:24 +0000 |
| commit | a4a5fa7fa591e91be86223f1fc8936d88255ac13 (patch) | |
| tree | d521d4fd4c45764e14e794e04ed7872fb15de33f /src/cpu/pred/ltage.cc | |
| parent | d8bc7899a97b85600e2e7ba12f2aec3d42fefc66 (diff) | |
| download | gem5-a4a5fa7fa591e91be86223f1fc8936d88255ac13.tar.xz | |
cpu: Fixed ratio of pred to hyst bits for LTAGE Bimodal
The LTAGE paper states 1 hyst bit shared for 4 pred bits.
Made this ratio configurable use 4 by default.
Also changed the Bimodal structure to use two std::vector<bool> (one for
pred and one for hyst bits)
Change-Id: I6793e8e358be01b75b8fd181ddad50f259862d79
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14120
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/pred/ltage.cc')
| -rw-r--r-- | src/cpu/pred/ltage.cc | 26 |
1 files changed, 16 insertions, 10 deletions
diff --git a/src/cpu/pred/ltage.cc b/src/cpu/pred/ltage.cc index 86b9e9993..874fbe41e 100644 --- a/src/cpu/pred/ltage.cc +++ b/src/cpu/pred/ltage.cc @@ -50,6 +50,7 @@ LTAGE::LTAGE(const LTAGEParams *params) : BPredUnit(params), logSizeBiMP(params->logSizeBiMP), + logRatioBiModalHystEntries(params->logRatioBiModalHystEntries), logSizeTagTables(params->logSizeTagTables), logSizeLoopPred(params->logSizeLoopPred), nHistoryTables(params->nHistoryTables), @@ -122,7 +123,11 @@ LTAGE::LTAGE(const LTAGEParams *params) } } - btable = new BimodalEntry[ULL(1) << logSizeBiMP]; + const uint64_t bimodalTableSize = ULL(1) << logSizeBiMP; + btablePrediction.resize(bimodalTableSize, false); + btableHysteresis.resize(bimodalTableSize >> logRatioBiModalHystEntries, + true); + ltable = new LoopEntry[ULL(1) << logSizeLoopPred]; gtable = new TageEntry*[nHistoryTables + 1]; for (int i = 1; i <= nHistoryTables; i++) { @@ -211,27 +216,28 @@ LTAGE::ctrUpdate(int8_t & ctr, bool taken, int nbits) bool LTAGE::getBimodePred(Addr pc, BranchInfo* bi) const { - return (btable[bi->bimodalIndex].pred > 0); + return btablePrediction[bi->bimodalIndex]; } -// Update the bimodal predictor: a hysteresis bit is shared among 4 prediction -// bits +// Update the bimodal predictor: a hysteresis bit is shared among N prediction +// bits (N = 2 ^ logRatioBiModalHystEntries) void LTAGE::baseUpdate(Addr pc, bool taken, BranchInfo* bi) { - int inter = (btable[bi->bimodalIndex].pred << 1) - + btable[bi->bimodalIndex ].hyst; + int inter = (btablePrediction[bi->bimodalIndex] << 1) + + btableHysteresis[bi->bimodalIndex >> logRatioBiModalHystEntries]; if (taken) { if (inter < 3) inter++; } else if (inter > 0) { inter--; } - btable[bi->bimodalIndex].pred = inter >> 1; - btable[bi->bimodalIndex].hyst = (inter & 1); - DPRINTF(LTage, "Updating branch %lx, pred:%d, hyst:%d\n", - pc, btable[bi->bimodalIndex].pred,btable[bi->bimodalIndex].hyst); + const bool pred = inter >> 1; + const bool hyst = inter & 1; + btablePrediction[bi->bimodalIndex] = pred; + btableHysteresis[bi->bimodalIndex >> logRatioBiModalHystEntries] = hyst; + DPRINTF(LTage, "Updating branch %lx, pred:%d, hyst:%d\n", pc, pred, hyst); } |