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authorAndreas Sandberg <Andreas.Sandberg@ARM.com>2014-08-13 06:57:31 -0400
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>2014-08-13 06:57:31 -0400
commit41d069ef6a46dddf118a7e480d27e70cc47d029d (patch)
treeefbe3a40685b749eedaae8e47fb932ff04354b08 /src/cpu/pred
parent8b8d991df053dad34cd490db6c8e7c94b5413290 (diff)
downloadgem5-41d069ef6a46dddf118a7e480d27e70cc47d029d.tar.xz
scons: Build the branch predictor for all CPUs
The branch predictor is normally only built when a CPU that uses a branch predictor is built. The list of CPUs is currently incomplete as the simple CPUs support branch predictors (for warming, branch stats, etc). In practice, all CPU models now use branch predictors, so this changeset removes the CPU model check and replaces it with a check for the NULL ISA.
Diffstat (limited to 'src/cpu/pred')
-rw-r--r--src/cpu/pred/SConscript23
1 files changed, 12 insertions, 11 deletions
diff --git a/src/cpu/pred/SConscript b/src/cpu/pred/SConscript
index bb9342f06..763f3a9b6 100644
--- a/src/cpu/pred/SConscript
+++ b/src/cpu/pred/SConscript
@@ -30,15 +30,16 @@
Import('*')
-if 'InOrderCPU' in env['CPU_MODELS'] or 'O3CPU' in env['CPU_MODELS'] \
- or 'Minor' in env['CPU_MODELS']:
- SimObject('BranchPredictor.py')
+if env['TARGET_ISA'] == 'null':
+ Return()
- Source('bpred_unit.cc')
- Source('2bit_local.cc')
- Source('btb.cc')
- Source('ras.cc')
- Source('tournament.cc')
- Source ('bi_mode.cc')
- DebugFlag('FreeList')
- DebugFlag('Branch')
+SimObject('BranchPredictor.py')
+
+Source('bpred_unit.cc')
+Source('2bit_local.cc')
+Source('btb.cc')
+Source('ras.cc')
+Source('tournament.cc')
+Source ('bi_mode.cc')
+DebugFlag('FreeList')
+DebugFlag('Branch')