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| author | Alec Roelke <ar4jc@virginia.edu> | 2017-11-10 12:23:43 -0500 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-11-29 01:05:24 +0000 |
| commit | 3f31abfbc84734dab86734c72bdca778575c26e5 (patch) | |
| tree | ab5e7c74b35c90c43c79cd5d40ba1f2751bbd05a /src/cpu/reg_class.hh | |
| parent | 719ddf73afa62735881ac68acf681abe1bf3bd17 (diff) | |
| download | gem5-3f31abfbc84734dab86734c72bdca778575c26e5.tar.xz | |
arch-riscv: Remove static parts of AMOs out of ISA
This patch removes the static parts of the RISC-V atomic memory
instructions out of the ISA generated code and into arch/riscv/insts. It
also makes the LR and SC instructions subclasses of MemInst from
arch/riscv/insts/mem.hh.
Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51
Reviewed-on: https://gem5-review.googlesource.com/6025
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/cpu/reg_class.hh')
0 files changed, 0 insertions, 0 deletions