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| author | Bradley Wang <radwang@ucdavis.edu> | 2018-07-19 18:23:29 -0700 |
|---|---|---|
| committer | Bradley Wang <radwang@ucdavis.edu> | 2018-08-10 23:41:23 +0000 |
| commit | cd913125d11b01a584ad08b32d988b786c42fe39 (patch) | |
| tree | 4bcf8021d9a355fb8afcbaa69fea034771ce8d40 /src/cpu/reg_class.hh | |
| parent | 1da285dfcc31b904afc27e440544d006aae25b38 (diff) | |
| download | gem5-cd913125d11b01a584ad08b32d988b786c42fe39.tar.xz | |
cpu: Removed unnecessary file reg_class_impl.hh
Previously, reg_class_impl.hh was added in order to prevent a cyclic
dependency between it and the_isa.hh (See
http://reviews.gem5.org/r/3754). It was determined that this was not
necessary. The two files had almost entirely the same includes, and the
current test-suite including multiple gcc and clang compilers on both
MacOS and Linux successfully built the library with all functionality
moved into the reg_class.hh file.
Change-Id: I0319e187b9eb280726a003951bb1ce315ffe17f5
Signed-off-by: Bradley Wang <radwang@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/11869
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/reg_class.hh')
| -rw-r--r-- | src/cpu/reg_class.hh | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh index 27bf59b19..def275ee4 100644 --- a/src/cpu/reg_class.hh +++ b/src/cpu/reg_class.hh @@ -131,7 +131,12 @@ class RegId { * constant zero value throughout the execution). */ - inline bool isZeroReg() const; + inline bool isZeroReg() const + { + return ((regClass == IntRegClass && regIdx == TheISA::ZeroReg) || + (THE_ISA == ALPHA_ISA && regClass == FloatRegClass && + regIdx == TheISA::ZeroReg)); + } /** @return true if it is an integer physical register. */ bool isIntReg() const { return regClass == IntRegClass; } @@ -167,7 +172,21 @@ class RegId { /** Index flattening. * Required to be able to use a vector for the register mapping. */ - inline RegIndex flatIndex() const; + inline RegIndex flatIndex() const + { + switch (regClass) { + case IntRegClass: + case FloatRegClass: + case VecRegClass: + case CCRegClass: + case MiscRegClass: + return regIdx; + case VecElemClass: + return Scale*regIdx + elemIdx; + } + panic("Trying to flatten a register without class!"); + return -1; + } /** @} */ /** Elem accessor */ |