cpu: Added interface for vector reg file

This patch adds some more functionality to the cpu model and the arch to
interface with the vector register file.

This change consists mainly of augmenting ThreadContexts and ExecContexts
with calls to get/set full vectors, underlying microarchitectural elements
or lanes. Those are meant to interface with the vector register file. All
classes that implement this interface also get an appropriate implementation.

This requires implementing the vector register file for the different
models using the VecRegContainer class.

This change set also updates the Result abstraction to contemplate the
possibility of having a vector as result.

The changes also affect how the remote_gdb connection works.

There are some (nasty) side effects, such as the need to define dummy
numPhysVecRegs parameter values for architectures that do not implement
vector extensions.

Nathanael Premillieu's work with an increasing number of fixes and
improvements of mine.

Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues and CC reg free list initialisation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2705

1 files changed, 40 insertions, 4 deletions

diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 05869e8fb..27bf59b19 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -39,6 +39,7 @@
  *
  * Authors: Steve Reinhardt
  *          Nathanael Premillieu
+ *          Rekai Gonzalez
  */
 
 #ifndef __CPU__REG_CLASS_HH__
@@ -55,6 +56,10 @@
 enum RegClass {
     IntRegClass,        ///< Integer register
     FloatRegClass,      ///< Floating-point register
+    /** Vector Register. */
+    VecRegClass,
+    /** Vector Register Native Elem lane. */
+    VecElemClass,
     CCRegClass,         ///< Condition-code register
     MiscRegClass        ///< Control (misc) register
 };
@@ -75,14 +80,27 @@ class RegId {
     static const char* regClassStrings[];
     RegClass regClass;
     RegIndex regIdx;
+    ElemIndex elemIdx;
+    static constexpr size_t Scale = TheISA::NumVecElemPerVecReg;
   public:
     RegId() {};
     RegId(RegClass reg_class, RegIndex reg_idx)
-        : regClass(reg_class), regIdx(reg_idx)
-    {}
+        : regClass(reg_class), regIdx(reg_idx), elemIdx(-1)
+    {
+        panic_if(regClass == VecElemClass,
+                "Creating vector physical index w/o element index");
+    }
+
+    explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx)
+        : regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx)
+    {
+        panic_if(regClass != VecElemClass,
+                "Creating non-vector physical index w/ element index");
+    }
 
     bool operator==(const RegId& that) const {
-        return regClass == that.classValue() && regIdx == that.index();
+        return regClass == that.classValue() && regIdx == that.index()
+                                             && elemIdx == that.elemIndex();
     }
 
     bool operator!=(const RegId& that) const {
@@ -94,7 +112,9 @@ class RegId {
      */
     bool operator<(const RegId& that) const {
         return regClass < that.classValue() ||
-                (regClass == that.classValue() && regIdx < that.index());
+            (regClass == that.classValue() && (
+                   regIdx < that.index() ||
+                   (regIdx == that.index() && elemIdx < that.elemIndex())));
     }
 
     /**
@@ -120,11 +140,25 @@ class RegId {
     bool isFloatReg() const { return regClass == FloatRegClass; }
 
     /** @Return true if it is a  condition-code physical register. */
+    bool isVecReg() const { return regClass == VecRegClass; }
+
+    /** @Return true if it is a  condition-code physical register. */
+    bool isVecElem() const { return regClass == VecElemClass; }
+
+    /** @Return true if it is a  condition-code physical register. */
     bool isCCReg() const { return regClass == CCRegClass; }
 
     /** @Return true if it is a  condition-code physical register. */
     bool isMiscReg() const { return regClass == MiscRegClass; }
 
+    /**
+     * Return true if this register can be renamed
+     */
+    bool isRenameable()
+    {
+        return regClass != MiscRegClass;
+    }
+
     /** Index accessors */
     /** @{ */
     const RegIndex& index() const { return regIdx; }
@@ -136,6 +170,8 @@ class RegId {
     inline RegIndex flatIndex() const;
     /** @} */
 
+    /** Elem accessor */
+    const RegIndex& elemIndex() const { return elemIdx; }
     /** Class accessor */
     const RegClass& classValue() const { return regClass; }
     /** Return a const char* with the register class name. */