cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.

1 files changed, 8 insertions, 1 deletions

diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index c9d4b1c4f..549ebab26 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -41,6 +41,7 @@
 enum RegClass {
     IntRegClass,        ///< Integer register
     FloatRegClass,      ///< Floating-point register
+    CCRegClass,         ///< Condition-code register
     MiscRegClass        ///< Control (misc) register
 };
 
@@ -72,9 +73,15 @@ RegClass regIdxToClass(TheISA::RegIndex reg_idx,
     if (reg_idx < TheISA::FP_Reg_Base) {
         cl = IntRegClass;
         offset = 0;
-    } else if (reg_idx < TheISA::Misc_Reg_Base) {
+    } else if (reg_idx < TheISA::CC_Reg_Base) {
         cl = FloatRegClass;
         offset = TheISA::FP_Reg_Base;
+    } else if (reg_idx < TheISA::Misc_Reg_Base) {
+        // if there are no CC regs, the ISA should set
+        // CC_Reg_Base == Misc_Reg_Base so the if above
+        // never succeeds
+        cl = CCRegClass;
+        offset = TheISA::CC_Reg_Base;
     } else {
         cl = MiscRegClass;
         offset = TheISA::Misc_Reg_Base;