cpu: Simplify the rename interface and use RegId

With the hierarchical RegId there are a lot of functions that are
redundant now.

The idea behind the simplification is that instead of having the regId,
telling which kind of register read/write/rename/lookup/etc. and then
the function panic_if'ing if the regId is not of the appropriate type,
we provide an interface that decides what kind of register to read
depending on the register type of the given regId.

Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2702

1 files changed, 61 insertions, 24 deletions

diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 25c882c58..05869e8fb 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -51,7 +51,7 @@
 #include "arch/registers.hh"
 #include "config/the_isa.hh"
 
-/// Enumerate the classes of registers.
+/** Enumerate the classes of registers. */
 enum RegClass {
     IntRegClass,        ///< Integer register
     FloatRegClass,      ///< Floating-point register
@@ -59,54 +59,91 @@ enum RegClass {
     MiscRegClass        ///< Control (misc) register
 };
 
-/// Number of register classes.  This value is not part of the enum,
-/// because putting it there makes the compiler complain about
-/// unhandled cases in some switch statements.
+/** Number of register classes.
+ * This value is not part of the enum, because putting it there makes the
+ * compiler complain about unhandled cases in some switch statements.
+ */
 const int NumRegClasses = MiscRegClass + 1;
 
-/// Register ID: describe an architectural register with its class and index.
-/// This structure is used instead of just the register index to disambiguate
-/// between different classes of registers.
-/// For example, a integer register with index 3 is represented by
-/// Regid(IntRegClass, 3).
-struct RegId {
+/** Register ID: describe an architectural register with its class and index.
+ * This structure is used instead of just the register index to disambiguate
+ * between different classes of registers. For example, a integer register with
+ * index 3 is represented by Regid(IntRegClass, 3).
+ */
+class RegId {
+  private:
+    static const char* regClassStrings[];
     RegClass regClass;
     RegIndex regIdx;
+  public:
     RegId() {};
     RegId(RegClass reg_class, RegIndex reg_idx)
         : regClass(reg_class), regIdx(reg_idx)
     {}
 
     bool operator==(const RegId& that) const {
-        return regClass == that.regClass && regIdx == that.regIdx;
+        return regClass == that.classValue() && regIdx == that.index();
     }
 
     bool operator!=(const RegId& that) const {
         return !(*this==that);
     }
 
-    /**
-     * Returns true if this register is a zero register (needs to have a
-     * constant zero value throughout the execution)
+    /** Order operator.
+     * The order is required to implement maps with key type RegId
      */
-    bool isZeroReg() const
-    {
-        return (regIdx == TheISA::ZeroReg &&
-                (regClass == IntRegClass ||
-                 (THE_ISA == ALPHA_ISA && regClass == FloatRegClass)));
+    bool operator<(const RegId& that) const {
+        return regClass < that.classValue() ||
+                (regClass == that.classValue() && regIdx < that.index());
     }
 
     /**
      * Return true if this register can be renamed
      */
-    bool isRenameable()
+    bool isRenameable() const
     {
         return regClass != MiscRegClass;
     }
 
-    static const RegId zeroReg;
-};
+    /**
+     * Check if this is the zero register.
+     * Returns true if this register is a zero register (needs to have a
+     * constant zero value throughout the execution).
+     */
+
+    inline bool isZeroReg() const;
 
-/// Map enum values to strings for debugging
-extern const char *RegClassStrings[];
+    /** @return true if it is an integer physical register. */
+    bool isIntReg() const { return regClass == IntRegClass; }
+
+    /** @return true if it is a floating-point physical register. */
+    bool isFloatReg() const { return regClass == FloatRegClass; }
+
+    /** @Return true if it is a  condition-code physical register. */
+    bool isCCReg() const { return regClass == CCRegClass; }
+
+    /** @Return true if it is a  condition-code physical register. */
+    bool isMiscReg() const { return regClass == MiscRegClass; }
+
+    /** Index accessors */
+    /** @{ */
+    const RegIndex& index() const { return regIdx; }
+    RegIndex& index() { return regIdx; }
+
+    /** Index flattening.
+     * Required to be able to use a vector for the register mapping.
+     */
+    inline RegIndex flatIndex() const;
+    /** @} */
+
+    /** Class accessor */
+    const RegClass& classValue() const { return regClass; }
+    /** Return a const char* with the register class name. */
+    const char* className() const { return regClassStrings[regClass]; }
+
+    friend std::ostream&
+    operator<<(std::ostream& os, const RegId& rid) {
+        return os << rid.className() << "{" << rid.index() << "}";
+    }
+};
 #endif // __CPU__REG_CLASS_HH__