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author | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
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committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
commit | 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch) | |
tree | 040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/cpu/reg_class.hh | |
parent | 552622184752dc798bc81f9b0b395db68aee9511 (diff) | |
download | gem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz |
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Diffstat (limited to 'src/cpu/reg_class.hh')
-rw-r--r-- | src/cpu/reg_class.hh | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh index c9d4b1c4f..549ebab26 100644 --- a/src/cpu/reg_class.hh +++ b/src/cpu/reg_class.hh @@ -41,6 +41,7 @@ enum RegClass { IntRegClass, ///< Integer register FloatRegClass, ///< Floating-point register + CCRegClass, ///< Condition-code register MiscRegClass ///< Control (misc) register }; @@ -72,9 +73,15 @@ RegClass regIdxToClass(TheISA::RegIndex reg_idx, if (reg_idx < TheISA::FP_Reg_Base) { cl = IntRegClass; offset = 0; - } else if (reg_idx < TheISA::Misc_Reg_Base) { + } else if (reg_idx < TheISA::CC_Reg_Base) { cl = FloatRegClass; offset = TheISA::FP_Reg_Base; + } else if (reg_idx < TheISA::Misc_Reg_Base) { + // if there are no CC regs, the ISA should set + // CC_Reg_Base == Misc_Reg_Base so the if above + // never succeeds + cl = CCRegClass; + offset = TheISA::CC_Reg_Base; } else { cl = MiscRegClass; offset = TheISA::Misc_Reg_Base; |