cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.

1 files changed, 5 insertions, 1 deletions

diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 549ebab26..6c7b1b55d 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -42,6 +42,7 @@ enum RegClass {
     IntRegClass,        ///< Integer register
     FloatRegClass,      ///< Floating-point register
     CCRegClass,         ///< Condition-code register
+    VectorRegClass,     ///< Vector register
     MiscRegClass        ///< Control (misc) register
 };
 
@@ -76,12 +77,15 @@ RegClass regIdxToClass(TheISA::RegIndex reg_idx,
     } else if (reg_idx < TheISA::CC_Reg_Base) {
         cl = FloatRegClass;
         offset = TheISA::FP_Reg_Base;
-    } else if (reg_idx < TheISA::Misc_Reg_Base) {
+    } else if (reg_idx < TheISA::Vector_Reg_Base) {
         // if there are no CC regs, the ISA should set
         // CC_Reg_Base == Misc_Reg_Base so the if above
         // never succeeds
         cl = CCRegClass;
         offset = TheISA::CC_Reg_Base;
+    } else if (reg_idx < TheISA::Misc_Reg_Base) {
+        cl = VectorRegClass;
+        offset = TheISA::Vector_Reg_Base;
     } else {
         cl = MiscRegClass;
         offset = TheISA::Misc_Reg_Base;