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| author | Nathan Binkert <nate@binkert.org> | 2007-08-12 09:56:37 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2007-08-12 09:56:37 -0700 |
| commit | 64295b800fd67e9b9bb3eee0131511a71ddf1fdb (patch) | |
| tree | ed1c759f11384dd2c263b43d7842be2922c5c39d /src/cpu/simple/AtomicSimpleCPU.py | |
| parent | b92594dd90f54a892771989a8164148e6647c9ab (diff) | |
| parent | ec4000e0e284834df0eb1db792074a1b11f21cc8 (diff) | |
| download | gem5-64295b800fd67e9b9bb3eee0131511a71ddf1fdb.tar.xz | |
merge
--HG--
extra : convert_revision : 5866eaa4008c4fa5da7fbb443132b8326955f71d
Diffstat (limited to 'src/cpu/simple/AtomicSimpleCPU.py')
| -rw-r--r-- | src/cpu/simple/AtomicSimpleCPU.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index e97f059c1..bfd1825c2 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -40,4 +40,5 @@ class AtomicSimpleCPU(BaseCPU): profile = Param.Latency('0ns', "trace the kernel stack") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") - _mem_ports = ['icache_port', 'dcache_port'] + physmem_port = Port("Physical Memory Port") + _mem_ports = ['icache_port', 'dcache_port', 'physmem_port'] |