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authorGabe Black <gblack@eecs.umich.edu>2007-11-12 14:38:24 -0800
committerGabe Black <gblack@eecs.umich.edu>2007-11-12 14:38:24 -0800
commitf17f3d20be08d25f176138691a29897df54e5cc0 (patch)
treeb10a30a948462b94c5f1b9001fb7dc314d32cf32 /src/cpu/simple/AtomicSimpleCPU.py
parent7a39457d7ff5fd80484061a4ff7006921899b229 (diff)
downloadgem5-f17f3d20be08d25f176138691a29897df54e5cc0.tar.xz
X86: Implement a page table walker.
--HG-- extra : convert_revision : 36bab5750100318faa9ba7178dc2e38590053aec
Diffstat (limited to 'src/cpu/simple/AtomicSimpleCPU.py')
-rw-r--r--src/cpu/simple/AtomicSimpleCPU.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index bfd1825c2..28c2aa9c9 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -41,4 +41,5 @@ class AtomicSimpleCPU(BaseCPU):
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
physmem_port = Port("Physical Memory Port")
- _mem_ports = ['icache_port', 'dcache_port', 'physmem_port']
+ _mem_ports = BaseCPU._mem_ports + \
+ ['icache_port', 'dcache_port', 'physmem_port']